include/opcode/

	* sparc.h: Document new format codes '4', '5', and '('.
	(OPF_LOW4, RS3): New macros.
opcodes/
	* sparc-dis.c (v9a_ast_reg_names): Add "cps".
	(X_RS3): New macro.
	(print_insn_sparc): Handle '4', '5', and '(' format codes.
	Accept %asr numbers below 28.
	* sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
	instructions.
gas/
	* config/tc-sparc.c (v9a_asr_table): Add "cps".
	(sparc_ip): Handle '4', '5' and '(' format codes.
gas/testsuite
	* gas/sparc/hpcvis3.d: New test.
	* gas/sparc/hpcvis3.s: New test source.
	* gas/sparc/sparc.exp: Run new test.

1 files changed, 18 insertions, 0 deletions

diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c
index a9d633d..61808f3 100644
--- a/gas/config/tc-sparc.c
+++ b/gas/config/tc-sparc.c
@@ -773,6 +773,7 @@ struct priv_reg_entry v9a_asr_table[] =
   {"pcr", 16},
   {"gsr", 19},
   {"dcr", 18},
+  {"cps", 28},
   {"clear_softint", 21},
   {"", -1},			/* End marker.  */
 };
@@ -2136,6 +2137,9 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
 	    case 'B':
 	    case 'R':
 
+	    case '4':
+	    case '5':
+
 	    case 'g':
 	    case 'H':
 	    case 'J':
@@ -2153,6 +2157,7 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
 
 		    if ((*args == 'v'
 			 || *args == 'B'
+			 || *args == '5'
 			 || *args == 'H')
 			&& (mask & 1))
 		      {
@@ -2214,6 +2219,11 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
 		    opcode |= RS2 (mask);
 		    continue;
 
+		  case '4':
+		  case '5':
+		    opcode |= RS3 (mask);
+		    continue;
+
 		  case 'g':
 		  case 'H':
 		  case 'J':
@@ -2233,6 +2243,14 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
 		}
 	      break;
 
+	    case '(':
+	      if (strncmp (s, "%efsr", 5) == 0)
+		{
+		  s += 5;
+		  continue;
+		}
+	      break;
+
 	    case '0':		/* 64 bit immediate (set, setsw, setx insn)  */
 	      the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere  */
 	      goto immediate;