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| author | Joern Rennecke <joern.rennecke@embecosm.com> | 2004-02-26 16:14:42 +0000 |
|---|---|---|
| committer | Joern Rennecke <joern.rennecke@embecosm.com> | 2004-02-26 16:14:42 +0000 |
| commit | 6a5709a5a18aabe5b4f7f14ddfd758af3eaa9a31 (patch) | |
| tree | 5cba78bb8d599578b49d7852b8b0152b3c172eee /gas/config/tc-sh.c | |
| parent | c89dc5d424056423307e7cd62896c5dc16e8d107 (diff) | |
| download | gdb-6a5709a5a18aabe5b4f7f14ddfd758af3eaa9a31.zip gdb-6a5709a5a18aabe5b4f7f14ddfd758af3eaa9a31.tar.gz gdb-6a5709a5a18aabe5b4f7f14ddfd758af3eaa9a31.tar.bz2 | |
2004-02-23 Andrew Stubbs <andrew.stubbs@superh.com>
gas:
* tc-sh.c (build_Mytes): Add REG_N_D and REG_N_B01
nibble types to assembler.
opcodes:
* sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
ensure that double registers have even numbers.
Add REG_N_B01 for nn01 (binary 01) nibble to ensure
that reserved instruction 0xfffd does not decode the same
as 0xfdfd (ftrv).
* sh-opc.h: Add REG_N_D nibble type and use it whereever
REG_N refers to a double register.
Add REG_N_B01 nibble type and use it instead of REG_NM
in ftrv.
Adjust the bit patterns in a few comments.
Diffstat (limited to 'gas/config/tc-sh.c')
| -rw-r--r-- | gas/config/tc-sh.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/gas/config/tc-sh.c b/gas/config/tc-sh.c index ee51c73..3e410e3 100644 --- a/gas/config/tc-sh.c +++ b/gas/config/tc-sh.c @@ -2142,6 +2142,7 @@ build_Mytes (sh_opcode_info *opcode, sh_operand_info *operand) switch (i) { case REG_N: + case REG_N_D: nbuf[index] = reg_n; break; case REG_M: @@ -2158,6 +2159,9 @@ build_Mytes (sh_opcode_info *opcode, sh_operand_info *operand) case REG_B: nbuf[index] = reg_b | 0x08; break; + case REG_N_B01: + nbuf[index] = reg_n | 0x01; + break; case IMM0_4BY4: insert (output + low_byte, BFD_RELOC_SH_IMM4BY4, 0, operand); break; |