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| author | Andrew Waterman <andrew@sifive.com> | 2016-12-18 22:53:50 -0800 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2016-12-20 12:26:34 +1030 |
| commit | 2922d21da14b4711872371abacb16e8ab7c70894 (patch) | |
| tree | 42987b9714a1c6641f3bc74c4a7e7230936545ff /gas/config/tc-riscv.h | |
| parent | 1d61f7949f77796ee407466f3ca7f42dcde9251b (diff) | |
| download | gdb-2922d21da14b4711872371abacb16e8ab7c70894.zip gdb-2922d21da14b4711872371abacb16e8ab7c70894.tar.gz gdb-2922d21da14b4711872371abacb16e8ab7c70894.tar.bz2 | |
Re-work RISC-V gas flags: now we just support -mabi and -march
We've decided to standardize on two flags for RISC-V: "-march" sets the
target architecture (which determines which instructions can be
generated), and "-mabi" sets the target ABI. We needed to rework this
because the old flag set didn't support soft-float or single-float ABIs,
and didn't support an x32-style ABI on RISC-V.
Additionally, we've changed the behavior of the -march flag: it's now a
lot stricter and only parses things we can actually understand.
Additionally, it's now lowercase-only: the rationale is that while the
RISC-V ISA manual specifies that ISA strings are case-insensitive, in
Linux-land things are usually case-sensitive. Since this flag can be
used to determine library paths, we didn't want to bake some
case-insensitivity in there that would case trouble later.
This patch implements these two new flags and removes the old flags that
could conflict with these. There wasn't a RISC-V release before, so we
want to just support a clean flag set.
include/
* elf/riscv.h (EF_RISCV_SOFT_FLOAT): Don't define.
(EF_RISCV_FLOAT_ABI, EF_RISCV_FLOAT_ABI_SOFT): Define.
(EF_RISCV_FLOAT_ABI_SINGLE, EF_RISCV_FLOAT_ABI_DOUBLE): Define.
(EF_RISCV_FLOAT_ABI_QUAD): Define.
bfd/
* elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Use
EF_RISCV_FLOAT_ABI_SOFT instead of EF_RISCV_SOFT_FLOAT.
binutils/
* readelf.c (get_machine_flags): Use
EF_RISCV_FLOAT_ABI_{SOFT,SINGLE,DOBULE,QUAD) instead of
EF_RISCV_{SOFT,HARD}_FLOAT.
gas/
* config/tc-riscv.h (xlen): Delete.
* config/tc-riscv.c (xlen): Make static.
(abi_xlen): New variable.
(options): Replace OPTION_{M32,M64,MSOFT_FLOAT,MHARD_FLOAT,MRVC}
with OPTION_MABI.
(md_longopts): Likewise.
(md_parse_option): Likewise.
(riscv_elf_final_processing): Likewise.
* doc/as.texinfo (Target RISC-V options): Likewise.
* doc/c-riscv.texi (OPTIONS): Likewise.
* config/tc-riscv.c (float_mode): Removed.
(float_abi): New type, specifies the floating-point ABI.
(riscv_set_abi): New function.
(riscv_add_subset): Only allow lower-case ISA names and require
them to start with "rv".
(riscv_after_parse_args): Likewise.
opcodes/
* riscv-dis.c (riscv_disassemble_insn): Default to the ELF's
XLEN when none is provided.
Diffstat (limited to 'gas/config/tc-riscv.h')
| -rw-r--r-- | gas/config/tc-riscv.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/gas/config/tc-riscv.h b/gas/config/tc-riscv.h index 32cf3ee..5e07fda 100644 --- a/gas/config/tc-riscv.h +++ b/gas/config/tc-riscv.h @@ -94,7 +94,6 @@ extern void riscv_cfi_frame_initial_instructions (void); #define tc_regname_to_dw2regnum tc_riscv_regname_to_dw2regnum extern int tc_riscv_regname_to_dw2regnum (char *); -extern unsigned xlen; #define DWARF2_DEFAULT_RETURN_COLUMN X_RA /* Even on RV64, use 4-byte alignment, as F registers may be only 32 bits. */ |