* configure.in: Recognise powerpc*le*, not just powerpcle*.

	* configure: Regenerate.
	* config/tc-ppc.c (PPC_LO, PPC_HI, PPC_HA, PPC_HIGHER,
	PPC_HIGHERA, PPC_HIGHEST, PPC_HIGHESTA, SEX16): New macros.
	(md_assemble): Use them.
	(ppc_machine): Support stub for ELF64 as well as XCOFF.
	(md_pseudo_table): Add "llong", "quad".
	(md_parse_option): Match default_cpu of powerpc*.
	(ppc_arch): Likewise.
	(ppc_subseg_align): Only for OBJ_XCOFF.
	(ppc_target_format): Return elf64-powerpc strings for 64 bit ELF.
	(md_begin): Select PPC_OPCODE_64 for 64 bit.
	(ppc_insert_operand): Don't bother testing 'file' before calling
	as_bad_where.  Use as_bad_where for operand->insert errors.
	(mapping): Add ELF64 relocation modifiers.
	(ppc_elf_suffix): Replace symbol on BFD_RELOC_PPC64_TOC reloc
	expressions with abs_symbol.
	(ppc_elf_cons): Correct offset for little endian targets.
	(ppc_elf_frob_symbol): New.
	(md_assemble): Add support for 64 bit ELF relocs.
	(ppc_tc): Ensure 8 byte alignment when 64 bit.
	(ppc_is_toc_sym): Only define for OBJ_XCOFF and OBJ_ELF.  Match
	".toc" section for 64 bit ELF.
	(ppc_fix_adjustable): New.  Macro body moved from tc-ppc.h.
	(md_apply_fix3): Silence warning with ATTRIBUTE_UNUSED.  Only do
	the ppc_is_toc_sym check for OBJ_XCOFF and OBJ_ELF.  For 64 bit,
	use BFD_RELOC_PPC64_TOC16_DS instead of BFD_RELOC_PPC_TOC16.
	Expand on comments, error message.  Add support for 64 bit relocs,
	and use PPC_HI etc. macros.
	* config/tc-ppc.h (MAX_MEM_FOR_RS_ALIGN_CODE): Define.
	(HANDLE_ALIGN): Define to generate nops in code sections rather
	than zeros.
	(TC_FORCE_RELOCATION): Force for BFD_RELOC_PPC64_TOC.
	(ELF_TC_SPECIAL_SECTIONS): Add 64 bit ELF sections.
	(tc_fix_adjustable): Move body of macro to tc-ppc.c.
	(ppc_fix_adjustable): Declare.
	(tc_frob_symbol): Define.
	(ppc_elf_frob_symbol): Declare.

1 files changed, 47 insertions, 16 deletions

diff --git a/gas/config/tc-ppc.h b/gas/config/tc-ppc.h
index c973d0c..a62147c 100644
--- a/gas/config/tc-ppc.h
+++ b/gas/config/tc-ppc.h
@@ -56,7 +56,7 @@ extern int target_big_endian;
 
 /* The target BFD format.  */
 #define TARGET_FORMAT (ppc_target_format ())
-extern char* ppc_target_format PARAMS ((void));
+extern char *ppc_target_format PARAMS ((void));
 
 /* Permit temporary numeric labels.  */
 #define LOCAL_LABELS_FB 1
@@ -84,6 +84,35 @@ extern char* ppc_target_format PARAMS ((void));
 
 /* We set the fx_done field appropriately in md_apply_fix.  */
 #define TC_HANDLES_FX_DONE
+
+#define MAX_MEM_FOR_RS_ALIGN_CODE 4
+#define HANDLE_ALIGN(FRAGP)						\
+  if ((FRAGP)->fr_type == rs_align_code) 				\
+    {									\
+      valueT count = ((FRAGP)->fr_next->fr_address			\
+		      - ((FRAGP)->fr_address + (FRAGP)->fr_fix));	\
+      if (count != 0 && (count & 3) == 0)				\
+	{								\
+	  unsigned char *dest = (FRAGP)->fr_literal + (FRAGP)->fr_fix;	\
+									\
+	  (FRAGP)->fr_var = 4;						\
+	  if (target_big_endian)					\
+	    {								\
+	      *dest++ = 0x60;						\
+	      *dest++ = 0;						\
+	      *dest++ = 0;						\
+	      *dest++ = 0;						\
+	    }								\
+	  else								\
+	    {								\
+	      *dest++ = 0;						\
+	      *dest++ = 0;						\
+	      *dest++ = 0;						\
+	      *dest++ = 0x60;						\
+	    }								\
+	}								\
+    }
+
 
 #ifdef TE_PE
 
@@ -197,6 +226,8 @@ do {								\
  || (FIXP)->fx_r_type == BFD_RELOC_PPC_B16_BRNTAKEN			\
  || (FIXP)->fx_r_type == BFD_RELOC_PPC_BA16_BRTAKEN			\
  || (FIXP)->fx_r_type == BFD_RELOC_PPC_BA16_BRNTAKEN			\
+ || (BFD_DEFAULT_TARGET_SIZE == 64					\
+     && (FIXP)->fx_r_type == BFD_RELOC_PPC64_TOC)			\
  || (FIXP)->fx_r_type == BFD_RELOC_VTABLE_INHERIT			\
  || (FIXP)->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
 
@@ -216,6 +247,12 @@ extern int ppc_section_flags PARAMS ((int, int, int));
 #define md_elf_section_word(STR, LEN)		ppc_section_word (STR, LEN)
 #define md_elf_section_flags(FLAGS, ATTR, TYPE)	ppc_section_flags (FLAGS, ATTR, TYPE)
 
+#if BFD_DEFAULT_TARGET_SIZE == 64
+/* Extra sections for 64-bit ELF PPC. */
+#define ELF_TC_SPECIAL_SECTIONS \
+  { ".toc",		SHT_PROGBITS,	SHF_ALLOC + SHF_WRITE}, \
+  { ".tocbss",		SHT_NOBITS,	SHF_ALLOC + SHF_WRITE},
+#else
 /* Add extra PPC sections -- Note, for now, make .sbss2 and .PPC.EMB.sbss0 a
    normal section, and not a bss section so that the linker doesn't crater
    when trying to make more than 2 sections.  */
@@ -227,26 +264,14 @@ extern int ppc_section_flags PARAMS ((int, int, int));
   { ".sbss2",		SHT_PROGBITS,	SHF_ALLOC }, \
   { ".PPC.EMB.sdata0",	SHT_PROGBITS,	SHF_ALLOC }, \
   { ".PPC.EMB.sbss0",	SHT_PROGBITS,	SHF_ALLOC },
+#endif
 
 #define tc_comment_chars ppc_comment_chars
 extern const char *ppc_comment_chars;
 
 /* Keep relocations relative to the GOT, or non-PC relative.  */
-#define tc_fix_adjustable(FIX)		\
-  ((FIX)->fx_r_type != BFD_RELOC_16_GOTOFF		\
-   && (FIX)->fx_r_type != BFD_RELOC_LO16_GOTOFF		\
-   && (FIX)->fx_r_type != BFD_RELOC_HI16_GOTOFF		\
-   && (FIX)->fx_r_type != BFD_RELOC_HI16_S_GOTOFF		\
-   && (FIX)->fx_r_type != BFD_RELOC_GPREL16		\
-   && (FIX)->fx_r_type != BFD_RELOC_VTABLE_INHERIT			\
-   && (FIX)->fx_r_type != BFD_RELOC_VTABLE_ENTRY			\
-   && ! S_IS_EXTERNAL ((FIX)->fx_addsy)					\
-   && ! S_IS_WEAK ((FIX)->fx_addsy)					\
-   && ((FIX)->fx_pcrel						\
-       || ((FIX)->fx_subsy != NULL					\
-	   && (S_GET_SEGMENT ((FIX)->fx_subsy)				\
-	       == S_GET_SEGMENT ((FIX)->fx_addsy)))			\
-       || S_IS_LOCAL ((FIX)->fx_addsy)))
+#define tc_fix_adjustable(fixp) ppc_fix_adjustable (fixp)
+extern int ppc_fix_adjustable PARAMS ((struct fix *));
 
 /* We must never ever try to resolve references to externally visible
    symbols in the assembler, because the .o file might go into a shared
@@ -258,6 +283,12 @@ extern const char *ppc_comment_chars;
        && S_IS_DEFINED ((FIX)->fx_addsy) \
        && ! S_IS_COMMON ((FIX)->fx_addsy)))
 
+#if BFD_DEFAULT_TARGET_SIZE == 64
+/* Finish up the symbol.  */
+#define tc_frob_symbol(sym, punt) punt = ppc_elf_frob_symbol (sym)
+extern int ppc_elf_frob_symbol PARAMS ((symbolS *));
+#endif
+
 #define DWARF2_LINE_MIN_INSN_LENGTH 4
 #endif /* OBJ_ELF */