Fix spelling mistakes and typos in the GAS sources.

	PR gas/21072
	* asintl.h: Fix spelling mistakes and typos.
	* atof-generic.c: Likewise.
	* bit_fix.h: Likewise.
	* config/atof-ieee.c: Likewise.
	* config/bfin-defs.h: Likewise.
	* config/bfin-parse.y: Likewise.
	* config/obj-coff-seh.h: Likewise.
	* config/obj-coff.c: Likewise.
	* config/obj-evax.c: Likewise.
	* config/obj-macho.c: Likewise.
	* config/rx-parse.y: Likewise.
	* config/tc-aarch64.c: Likewise.
	* config/tc-alpha.c: Likewise.
	* config/tc-arc.c: Likewise.
	* config/tc-arm.c: Likewise.
	* config/tc-avr.c: Likewise.
	* config/tc-bfin.c: Likewise.
	* config/tc-cr16.c: Likewise.
	* config/tc-cris.c: Likewise.
	* config/tc-crx.c: Likewise.
	* config/tc-d10v.c: Likewise.
	* config/tc-d30v.c: Likewise.
	* config/tc-dlx.c: Likewise.
	* config/tc-epiphany.c: Likewise.
	* config/tc-frv.c: Likewise.
	* config/tc-hppa.c: Likewise.
	* config/tc-i370.c: Likewise.
	* config/tc-i386-intel.c: Likewise.
	* config/tc-i386.c: Likewise.
	* config/tc-i960.c: Likewise.
	* config/tc-ia64.c: Likewise.
	* config/tc-m32r.c: Likewise.
	* config/tc-m68hc11.c: Likewise.
	* config/tc-m68k.c: Likewise.
	* config/tc-mcore.c: Likewise.
	* config/tc-mep.c: Likewise.
	* config/tc-mep.h: Likewise.
	* config/tc-metag.c: Likewise.
	* config/tc-microblaze.c: Likewise.
	* config/tc-mips.c: Likewise.
	* config/tc-mmix.c: Likewise.
	* config/tc-mn10200.c: Likewise.
	* config/tc-mn10300.c: Likewise.
	* config/tc-msp430.c: Likewise.
	* config/tc-msp430.h: Likewise.
	* config/tc-nds32.c: Likewise.
	* config/tc-nds32.h: Likewise.
	* config/tc-nios2.c: Likewise.
	* config/tc-nios2.h: Likewise.
	* config/tc-ns32k.c: Likewise.
	* config/tc-pdp11.c: Likewise.
	* config/tc-ppc.c: Likewise.
	* config/tc-pru.c: Likewise.
	* config/tc-rx.c: Likewise.
	* config/tc-s390.c: Likewise.
	* config/tc-score.c: Likewise.
	* config/tc-score7.c: Likewise.
	* config/tc-sh.c: Likewise.
	* config/tc-sh64.c: Likewise.
	* config/tc-sparc.c: Likewise.
	* config/tc-tic4x.c: Likewise.
	* config/tc-tic54x.c: Likewise.
	* config/tc-v850.c: Likewise.
	* config/tc-vax.c: Likewise.
	* config/tc-visium.c: Likewise.
	* config/tc-xgate.c: Likewise.
	* config/tc-xtensa.c: Likewise.
	* config/tc-z80.c: Likewise.
	* config/tc-z8k.c: Likewise.
	* config/te-vms.c: Likewise.
	* config/xtensa-relax.c: Likewise.
	* doc/as.texinfo: Likewise.
	* doc/c-arm.texi: Likewise.
	* doc/c-hppa.texi: Likewise.
	* doc/c-i370.texi: Likewise.
	* doc/c-i386.texi: Likewise.
	* doc/c-m32r.texi: Likewise.
	* doc/c-m68k.texi: Likewise.
	* doc/c-mmix.texi: Likewise.
	* doc/c-msp430.texi: Likewise.
	* doc/c-nds32.texi: Likewise.
	* doc/c-ns32k.texi: Likewise.
	* doc/c-riscv.texi: Likewise.
	* doc/c-rx.texi: Likewise.
	* doc/c-s390.texi: Likewise.
	* doc/c-tic6x.texi: Likewise.
	* doc/c-tilegx.texi: Likewise.
	* doc/c-tilepro.texi: Likewise.
	* doc/c-v850.texi: Likewise.
	* doc/c-xgate.texi: Likewise.
	* doc/c-xtensa.texi: Likewise.
	* dwarf2dbg.c: Likewise.
	* ecoff.c: Likewise.
	* itbl-ops.c: Likewise.
	* listing.c: Likewise.
	* macro.c: Likewise.
	* po/gas.pot: Likewise.
	* read.c: Likewise.
	* struc-symbol.h: Likewise.
	* symbols.h: Likewise.
	* testsuite/gas/arc/relocs-errors.err: Likewise.
	* write.c: Likewise.

1 files changed, 30 insertions, 30 deletions

diff --git a/gas/config/tc-nds32.c b/gas/config/tc-nds32.c
index 3d8034e..19431b4 100644
--- a/gas/config/tc-nds32.c
+++ b/gas/config/tc-nds32.c
@@ -3409,24 +3409,24 @@ nds32_seg (int i)
 }
 
 /* Set if label adjustment is needed.  I should not adjust .xbyte in dwarf.  */
-static symbolS *nds32_last_label;	/* Last label for aligment.  */
+static symbolS *nds32_last_label;	/* Last label for alignment.  */
 
-/* This code is referred from D30V for adjust label to be with pedning
-   aligment.  For example,
+/* This code is referred from D30V for adjust label to be with pending
+   alignment.  For example,
      LBYTE: .byte	0x12
      LHALF: .half	0x12
      LWORD: .word	0x12
-   Without this, the above label will not attatch to incoming data.  */
+   Without this, the above label will not attach to incoming data.  */
 
 static void
 nds32_adjust_label (int n)
 {
-  /* FIXME: I think adjust lable and alignment is
-     the programmer's obligation.  Saddly, VLSI team doesn't
+  /* FIXME: I think adjust label and alignment is
+     the programmer's obligation.  Sadly, VLSI team doesn't
      properly use .align for their test cases.
      So I re-implement cons_align and auto adjust labels, again.
 
-     I think d30v's implmentation is simple and good enough.  */
+     I think d30v's implementation is simple and good enough.  */
 
   symbolS *label = nds32_last_label;
   nds32_last_label = NULL;
@@ -3493,7 +3493,7 @@ nds32_cons_align (int size ATTRIBUTE_UNUSED)
 
      There are two things should be done for auto-adjust-label.
      1. Align data/instructions and adjust label to be attached to them.
-     2. Clear auto-adjust state, so incommng data/instructions will not
+     2. Clear auto-adjust state, so incoming data/instructions will not
 	adjust the label.
 
      For example,
@@ -3919,7 +3919,7 @@ nds32_pre_do_align (int n, char *fill, int len, int max)
 	      fragP = frag_now;
 	      frag_align_code (n, max);
 
-	      /* Tag this alignment when there is a lable before it.  */
+	      /* Tag this alignment when there is a label before it.  */
 	      if (label_exist)
 		{
 		  fragP->tc_frag_data.flag = NDS32_FRAG_LABEL;
@@ -4011,7 +4011,7 @@ md_begin (void)
   asm_desc.parse_operand = nds32_asm_parse_operand;
   nds32_asm_init (&asm_desc, 0);
 
-  /* Initial general pupose registers hash table.  */
+  /* Initial general purpose registers hash table.  */
   nds32_gprs_hash = hash_new ();
   for (k = keyword_gpr; k->name; k++)
     hash_insert (nds32_gprs_hash, k->name, k);
@@ -4656,7 +4656,7 @@ static struct nds32_hint_map hint_map [] =
     },
     {
       /* LONGJUMP5.  */
-      /* There is two kinds of veriation of LONGJUMP5.  One of them
+      /* There is two kinds of variations of LONGJUMP5.  One of them
 	 generate EMPTY relocation for converted INSN16 if needed.
 	 But we don't distinguish them here.  */
       _dummy_first_bfd_reloc_code_real,
@@ -4816,7 +4816,7 @@ nds32_find_reloc_table (struct nds32_relocs_pattern *relocs_pattern,
 
   if (map_ptr->insn_list == 0)
     {
-      as_warn (_("Can not find match relax hint. line : %d"),
+      as_warn (_("Can not find match relax hint.  Line: %d"),
 	       relocs_pattern->frag->fr_line);
       return FALSE;
     }
@@ -4868,7 +4868,7 @@ nds32_find_reloc_table (struct nds32_relocs_pattern *relocs_pattern,
     }
   /* Clear final relocation.  */
   memset (hint_fixup, 0, sizeof (nds32_relax_fixup_info_t));
-  /* Copy code sequance.  */
+  /* Copy code sequence.  */
   memcpy (hint_code, code_seq, seq_size);
   return TRUE;
 }
@@ -5150,7 +5150,7 @@ nds32_check_insn_available (struct nds32_asm_insn insn, const char *str)
 
   if  ((baseline_isa & attr) == 0)
     {
-      as_bad (_("Not support instrcution %s in the baseline."), str);
+      as_bad (_("Instruction %s not supported in the baseline."), str);
       return FALSE;
     }
   return TRUE;
@@ -5247,7 +5247,7 @@ md_assemble (char *str)
     {
       /* User assembly code branch relax for it.  */
       /* If fld is not NULL, it is a symbol.  */
-      /* Branch msut relax to proper pattern in user assembly code exclude
+      /* Branch must relax to proper pattern in user assembly code exclude
 	 J and JAL.  Keep these two in original type for users which wants
 	 to keep their size be fixed.  In general, assembler does not convert
 	 instruction generated by compiler.  But jump instruction may be
@@ -5304,7 +5304,7 @@ md_assemble (char *str)
       fragP->tc_frag_data.insn = insn.insn;
       fragP->fr_fix += 2;
 
-      /* In original, we don't relax the instrucion with label on it,
+      /* In original, we don't relax the instruction with label on it,
 	 but this may cause some redundant nop16.  Therefore, tag this
 	 relaxable instruction and relax it carefully.  */
       if (label)
@@ -5322,7 +5322,7 @@ md_assemble (char *str)
       expressionS exp;
       out = frag_var (rs_machine_dependent, insn.opcode->isize,
 		      0, 0, NULL, 0, NULL);
-      /* If this insturction is branch target, it is not relaxable.  */
+      /* If this instruction is branch target, it is not relaxable.  */
       fragP->tc_frag_data.flag = NDS32_FRAG_LABEL;
       fragP->tc_frag_data.opcode = insn.opcode;
       fragP->tc_frag_data.insn = insn.insn;
@@ -5478,7 +5478,7 @@ nds32_convert_to_range_type (long offset)
   return range_type;
 }
 
-/* Set insntruction register mask.  */
+/* Set instruction register mask.  */
 
 static void
 nds32_elf_get_set_cond (relax_info_t *relax_info, int offset, uint32_t *insn,
@@ -5529,7 +5529,7 @@ nds32_relax_branch_instructions (segT segment, fragS *fragP,
   if (fragP->fr_symbol == NULL)
     return adjust;
 
-  /* If frag_var is not enough room, the previos frag is fr_full and with
+  /* If frag_var is not enough room, the previous frag is fr_full and with
      opcode.  The new one is rs_dependent but without opcode.  */
   if (opcode == NULL)
     return adjust;
@@ -5659,13 +5659,13 @@ invalid_prev_frag (fragS * fragP, fragS **prev_frag)
 	  || frag_t->fr_type == rs_align_code
 	  || frag_t->fr_type == rs_align_test)
 	{
-	  /* Relax instruction can not walk across lable.  */
+	  /* Relax instruction can not walk across label.  */
 	  if (frag_t->tc_frag_data.flag & NDS32_FRAG_LABEL)
 	    {
 	      prev_frag = NULL;
 	      return;
 	    }
-	  /* Relax previos relaxable to align rs_align frag.  */
+	  /* Relax previous relaxable to align rs_align frag.  */
 	  address = frag_t->fr_address + frag_t->fr_fix;
 	  addressT offset = nds32_get_align (address, (int) frag_t->fr_offset);
 	  if (offset & 0x2)
@@ -5720,8 +5720,8 @@ nds32_relax_frag (segT segment, fragS *fragP, long stretch ATTRIBUTE_UNUSED)
   if (fragP->tc_frag_data.flag & NDS32_FRAG_RELAXABLE
       && (fragP->tc_frag_data.flag & NDS32_FRAG_RELAXED) == 0)
     /* Here is considered relaxed case originally.  But it may cause
-       unendless loop when relaxing.  Once the instruction is relaxed,
-       it can not be undo.  */
+       an endless loop when relaxing.  Once the instruction is relaxed,
+       it can not be undone.  */
     prev_frag = fragP;
 
   return adjust;
@@ -5744,7 +5744,7 @@ md_estimate_size_before_relax (fragS *fragP, segT segment)
      1. relax for branch
      2. relax for 32-bits to 16-bits  */
 
-  /* Save previos relaxable frag.  */
+  /* Save previous relaxable frag.  */
   static fragS *prev_frag = NULL;
   int adjust = 0;
 
@@ -5803,7 +5803,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragP)
   if (branch_symbol == NULL && !(fragP->tc_frag_data.flag & NDS32_FRAG_RELAXED))
     return;
 
-  /* If frag_var is not enough room, the previos frag is fr_full and with
+  /* If frag_var is not enough room, the previous frag is fr_full and with
      opcode.  The new one is rs_dependent but without opcode.  */
   if (opcode == NULL)
     return;
@@ -5921,7 +5921,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT sec, fragS *fragP)
 				  origin_insn, branch_range_type);
 
 	  /* Try to convert to 16-bits instruction.  Currently, only the first
-	     insntruction in pattern can be converted.  EX: bnez sethi ori jr,
+	     instruction in pattern can be converted.  EX: bnez sethi ori jr,
 	     only bnez can be converted to 16 bit and ori can't.  */
 
 	  while (fixup_info[k].size != 0
@@ -6224,7 +6224,7 @@ nds32_insert_relax_entry (bfd *abfd ATTRIBUTE_UNUSED, asection *sec,
   else
     {
       /* These flags are only enabled when global relax is enabled.
-	 Maybe we can check DISABLE_RELAX_FLAG at linke-time,
+	 Maybe we can check DISABLE_RELAX_FLAG at link-time,
 	 so we set them anyway.  */
       if (enable_relax_ex9)
 	exp.X_add_number |= R_NDS32_RELAX_ENTRY_EX9_FLAG;
@@ -6464,7 +6464,7 @@ nds32_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
       fixP->tc_fix_data = NULL;
 
       /* Transform specific relocations here for later relocation generation.
-	 Tag data here for ex9 relaxtion and tag tls data for linker.  */
+	 Tag data here for ex9 relaxation and tag tls data for linker.  */
       switch (fixP->fx_r_type)
 	{
 	case BFD_RELOC_NDS32_DATA:
@@ -6519,7 +6519,7 @@ nds32_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
 	 ---- 8< ---- 8< ---- 8< ---- 8< ----
 
 	 We use a single relocation entry for this expression.
-	 * The initial distance value is stored direcly in that location
+	 * The initial distance value is stored directly in that location
 	   specified by r_offset (i.e., foo in this example.)
 	 * The begin of the region, i.e., .LBEGIN, is specified by
 	   r_info/R_SYM and r_addend, e.g., .text + 0x32.
@@ -6686,7 +6686,7 @@ nds32_parse_name (char const *name, expressionS *exprP,
   exprP->X_op = O_symbol;
   exprP->X_add_number = 0;
 
-  /* Check the specail name if a symbol.  */
+  /* Check the special name if a symbol.  */
   segment = S_GET_SEGMENT (exprP->X_add_symbol);
   if (segment != undefined_section)
     return 0;