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authorRobert Suchanek <robert.suchanek@imgtec.com>2015-07-28 11:26:39 +0100
committerRobert Suchanek <robert.suchanek@imgtec.com>2015-07-28 11:26:39 +0100
commitc6e5c03a2c0dfa224a71056ede035476e511f5fc (patch)
tree185ce4ae518db00cafbac0f00a4d95823c99163d /gas/config/tc-mips.c
parent77403ce9669d35b286b3ca75fdc1e4c61f36b59a (diff)
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Add cores for M5100 series
gas/ * config/tc-mips.c (mips_cpu_info_table): Add m5100 and m5101 entries. * doc/c-mips.texi: Document m5100 and m5101 for -march=.
Diffstat (limited to 'gas/config/tc-mips.c')
-rw-r--r--gas/config/tc-mips.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 907fafd..45126fe 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -18668,6 +18668,9 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
{ "1004kf1_1", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
/* interaptiv is the new name for 1004kf */
{ "interaptiv", 0, ASE_DSP | ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 },
+ /* M5100 family */
+ { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
+ { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 },
/* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */
{ "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 },