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| author | Maciej W. Rozycki <macro@imgtec.com> | 2016-05-20 12:41:50 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@imgtec.com> | 2016-05-20 12:41:50 +0100 |
| commit | 134c0c8bf4a258ba10e72b724eadf40f731bb7ec (patch) | |
| tree | 55a081bb5c86b954a48a03a661bbef98792e8e96 /gas/config/tc-mips.c | |
| parent | d310f46e3343f2575465fed65079fc6912dee9cf (diff) | |
| download | gdb-134c0c8bf4a258ba10e72b724eadf40f731bb7ec.zip gdb-134c0c8bf4a258ba10e72b724eadf40f731bb7ec.tar.gz gdb-134c0c8bf4a258ba10e72b724eadf40f731bb7ec.tar.bz2 | |
MIPS/GAS: Correct tab-after-space formatting mistakes
* config/tc-mips.c: Correct tab-after-space formatting mistakes
throughout.
Diffstat (limited to 'gas/config/tc-mips.c')
| -rw-r--r-- | gas/config/tc-mips.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index b538ff0..ccdda0c 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -349,7 +349,7 @@ static int mips_32bitmode = 0; /* Likewise 64-bit registers. */ #define ABI_NEEDS_64BIT_REGS(ABI) \ - ((ABI) == N32_ABI \ + ((ABI) == N32_ABI \ || (ABI) == N64_ABI \ || (ABI) == O64_ABI) @@ -1017,7 +1017,7 @@ static int mips_relax_branch; /* Branch without likely bit. If label is out of range, we turn: - beq reg1, reg2, label + beq reg1, reg2, label delay slot into @@ -6273,8 +6273,8 @@ nops_for_vr4130 (int ignore, const struct mips_cl_insn *hist, return 0; } -#define BASE_REG_EQ(INSN1, INSN2) \ - ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ +#define BASE_REG_EQ(INSN1, INSN2) \ + ((((INSN1) >> OP_SH_RS) & OP_MASK_RS) \ == (((INSN2) >> OP_SH_RS) & OP_MASK_RS)) /* Return the minimum alignment for this store instruction. */ @@ -11044,7 +11044,7 @@ macro (struct mips_cl_insn *ip, char *str) if (mips_opts.noreorder) macro_build (NULL, "nop", ""); expr1.X_add_number = mips_cprestore_offset; - macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, + macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, mips_gp_register, mips_frame_reg, HAVE_64BIT_ADDRESSES); @@ -11188,7 +11188,7 @@ macro (struct mips_cl_insn *ip, char *str) if (mips_opts.noreorder) macro_build (NULL, "nop", ""); expr1.X_add_number = mips_cprestore_offset; - macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, + macro_build_ldst_constoffset (&expr1, ADDRESS_LOAD_INSN, mips_gp_register, mips_frame_reg, HAVE_64BIT_ADDRESSES); @@ -12145,8 +12145,8 @@ macro (struct mips_cl_insn *ip, char *str) && offset_expr.X_add_number == 0); s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); if (strcmp (s, ".lit8") == 0) - { - op[2] = mips_gp_register; + { + op[2] = mips_gp_register; offset_reloc[0] = BFD_RELOC_MIPS_LITERAL; offset_reloc[1] = BFD_RELOC_UNUSED; offset_reloc[2] = BFD_RELOC_UNUSED; @@ -12168,7 +12168,7 @@ macro (struct mips_cl_insn *ip, char *str) offset_reloc[0] = BFD_RELOC_LO16; offset_reloc[1] = BFD_RELOC_UNUSED; offset_reloc[2] = BFD_RELOC_UNUSED; - } + } align = 8; /* Fall through */ @@ -16449,7 +16449,7 @@ s_nan (int ignore ATTRIBUTE_UNUSED) directive, such as in: foo: - .stabs ... + .stabs ... .set mips16 so the current mode wins. */ @@ -18714,7 +18714,7 @@ static const struct mips_cpu_info mips_cpu_info_table[] = { "m5100", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, { "m5101", 0, ASE_MCU, ISA_MIPS32R5, CPU_MIPS32R5 }, /* P5600 with EVA and Virtualization ASEs, other ASEs are optional. */ - { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 }, + { "p5600", 0, ASE_VIRT | ASE_EVA | ASE_XPA, ISA_MIPS32R5, CPU_MIPS32R5 }, /* MIPS 64 */ { "5kc", 0, 0, ISA_MIPS64, CPU_MIPS64 }, |