Add load-link, store-conditional paired EVA instructions

Add paired load-link and store-conditional instructions to the
EVA ASE for MIPS32R6[1].  These instructions are optional within
the EVA ASE.  Their presence is indicated by the XNP bit in the
Config5 register.

[1] "MIPS Architecture for Programmers Volume II-A: The MIPS32
     Instruction Set Manual", Imagination Technologies Ltd., Document
     Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2
     "Alphabetical List of Instructions", pp. 230-231, pp. 357-360.

gas/
	* config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6.
	(macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases.
	(mips_after_parse_args): Translate EVA to EVA_R6.
	* testsuite/gas/mips/ase-errors-1.s: Add new instructions.
	* testsuite/gas/mips/eva.s: Likewise.
	* testsuite/gas/mips/ase-errors-1.l: Check errors for
	 new instructions.
	* testsuite/gas/mips/mipsr6@eva.d: Check new test cases.

include/
	* opcode/mips.h (ASE_EVA_R6): New macro.
	(M_LLWPE_AB, M_SCWPE_AB): New enum values.

opcodes/
	* mips-dis.c (mips_calculate_combination_ases): Add ISA
	argument and set ASE_EVA_R6 appropriately.
	(set_default_mips_dis_options): Pass ISA to above.
	(parse_mips_dis_option): Likewise.
	* mips-opc.c (EVAR6): New macro.
	(mips_builtin_opcodes): Add llwpe, scwpe.

Derived from patch authored by Andrew Bennett <andrew.bennett@imgtec.com>

1 files changed, 18 insertions, 1 deletions

diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 091ea7b..6a945e3 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -2227,7 +2227,7 @@ mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts,
 
   /* Clear combination ASE flags, which need to be recalculated based on
      updated regular ASE settings.  */
-  opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT);
+  opts->ase &= ~(ASE_MIPS16E2_MT | ASE_XPA_VIRT | ASE_EVA_R6);
 
   if (enabled_p)
     opts->ase |= ase->flags;
@@ -2246,6 +2246,15 @@ mips_set_ase (const struct mips_ase *ase, struct mips_set_options *opts,
       mask |= ASE_MIPS16E2_MT;
     }
 
+  /* The EVA Extension has instructions which are only valid when the R6 ISA
+     is enabled.  This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are
+     present.  */
+  if (((opts->ase & ASE_EVA) != 0) && ISA_IS_R6 (opts->isa))
+    {
+      opts->ase |= ASE_EVA_R6;
+      mask |= ASE_EVA_R6;
+    }
+
   return mask;
 }
 
@@ -12017,6 +12026,7 @@ macro (struct mips_cl_insn *ip, char *str)
       goto ld;
     case M_LLDP_AB:
     case M_LLWP_AB:
+    case M_LLWPE_AB:
       s = ip->insn_mo->name;
       fmt = "t,d,s";
       ll_sc_paired = 1;
@@ -12125,6 +12135,7 @@ macro (struct mips_cl_insn *ip, char *str)
       goto ld_st;
     case M_SCDP_AB:
     case M_SCWP_AB:
+    case M_SCWPE_AB:
       s = ip->insn_mo->name;
       fmt = "t,d,s";
       ll_sc_paired = 1;
@@ -15246,6 +15257,12 @@ mips_after_parse_args (void)
   file_mips_opts.isa = arch_info->isa;
   file_mips_opts.init_ase = arch_info->ase;
 
+  /* The EVA Extension has instructions which are only valid when the R6 ISA
+     is enabled.  This sets the ASE_EVA_R6 flag when both EVA and R6 ISA are
+     present.  */
+  if (((file_mips_opts.ase & ASE_EVA) != 0) && ISA_IS_R6 (file_mips_opts.isa))
+    file_mips_opts.ase |= ASE_EVA_R6;
+
   /* Set up initial mips_opts state.  */
   mips_opts = file_mips_opts;