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| author | Thiemo Seufer <ths@networkno.de> | 2006-11-06 14:28:21 +0000 |
|---|---|---|
| committer | Thiemo Seufer <ths@networkno.de> | 2006-11-06 14:28:21 +0000 |
| commit | a360e743fba30ffcd20ca3878b16bc28b5634629 (patch) | |
| tree | 4483e232ad8c5b8c5b049cd595cadcc316dfb34c /gas/config/tc-mips.c | |
| parent | 7d0317c40ffffb902c5661b7cf62758831ed62d5 (diff) | |
| download | gdb-a360e743fba30ffcd20ca3878b16bc28b5634629.zip gdb-a360e743fba30ffcd20ca3878b16bc28b5634629.tar.gz gdb-a360e743fba30ffcd20ca3878b16bc28b5634629.tar.bz2 | |
* config/tc-mips.c (mips_cpu_info_table): Remove 24k/24ke aliases.
34k always has DSP ASE.
Diffstat (limited to 'gas/config/tc-mips.c')
| -rw-r--r-- | gas/config/tc-mips.c | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index e9657c1..d3ed818 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -14580,19 +14580,20 @@ static const struct mips_cpu_info mips_cpu_info_table[] = { "4ksd", MIPS_CPU_ASE_SMARTMIPS, ISA_MIPS32R2, CPU_MIPS32R2 }, { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, - { "24k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, /* 24ke is a 24k with DSP ASE, other ASEs are optional. */ - { "24ke", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, - /* 34k is a 24k with MT ASE, other ASEs are optional. */ - { "34kc", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, - { "34kf", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, - { "34kx", MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, + /* 34k is a 24k with DSP and MT ASE, other ASEs are optional. */ + { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, + ISA_MIPS32R2, CPU_MIPS32R2 }, + { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, + ISA_MIPS32R2, CPU_MIPS32R2 }, + { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, + ISA_MIPS32R2, CPU_MIPS32R2 }, /* MIPS 64 */ { "5kc", 0, ISA_MIPS64, CPU_MIPS64 }, |