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| author | Richard Sandiford <rdsandiford@googlemail.com> | 2013-02-09 10:24:20 +0000 |
|---|---|---|
| committer | Richard Sandiford <rdsandiford@googlemail.com> | 2013-02-09 10:24:20 +0000 |
| commit | 0aa27725e5ee24a1d2e11e661f1ad85d57cd5da8 (patch) | |
| tree | d1734f20e5dda35502bd618c4e4f55aa68b6aee0 /gas/config/tc-mips.c | |
| parent | 797f89476b3e9ecb7c77da4d3338a47fbba43019 (diff) | |
| download | gdb-0aa27725e5ee24a1d2e11e661f1ad85d57cd5da8.zip gdb-0aa27725e5ee24a1d2e11e661f1ad85d57cd5da8.tar.gz gdb-0aa27725e5ee24a1d2e11e661f1ad85d57cd5da8.tar.bz2 | |
gas/
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
* config/tc-mips.c (CPU_HAS_LDC1_SDC1): New macro.
(macro): Use it. Assert that trunc.w.s is not used for r5900.
opcodes/
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
* mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
single-float. Disable ll, lld, sc and scd for EE. Disable the
trunc.w.s macro for EE.
gas/testsuite/
2013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
* gas/mips/24k-triple-stores-2.d, gas/mips/24k-triple-stores-2.s,
gas/mips/micromips@24k-triple-stores-2.d: Move "sc" tests to...
* gas/mips/24k-triple-stores-2-llsc.d,
gas/mips/24k-triple-stores-2-llsc.s,
gas/mips/micromips@24k-triple-stores-2-llsc.d: ...these new tests.
* gas/mips/r5900-full.d, gas/mips/r5900-full.s: Verify that the
MIPS ISA level can be upgraded to support ll, sc, lld and scd.
* gas/mips/l_d-single.d, gas/mips/s_d-single.d,
gas/mips/r5900-nollsc.l, gas/mips/r5900-nollsc.s: New tests.
* gas/mips/mips.exp: Update accordingly. Add "nollsc" to r5900
properties.
Diffstat (limited to 'gas/config/tc-mips.c')
| -rw-r--r-- | gas/config/tc-mips.c | 21 |
1 files changed, 11 insertions, 10 deletions
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 67f04aa..964efdd 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -504,6 +504,10 @@ static int mips_32bitmode = 0; /* True if CPU has seq/sne and seqi/snei instructions. */ #define CPU_HAS_SEQ(CPU) (CPU_IS_OCTEON (CPU)) +/* True, if CPU has support for ldc1 and sdc1. */ +#define CPU_HAS_LDC1_SDC1(CPU) \ + ((mips_opts.isa != ISA_MIPS1) && ((CPU) != CPU_R5900)) + /* True if mflo and mfhi can be immediately followed by instructions which write to the HI and LO registers. @@ -8927,8 +8931,7 @@ macro (struct mips_cl_insn *ip) s = segment_name (S_GET_SEGMENT (offset_expr.X_add_symbol)); if (strcmp (s, ".lit8") == 0) { - if ((mips_opts.isa != ISA_MIPS1 || mips_opts.micromips) - && (mips_opts.arch != CPU_R5900)) + if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips) { macro_build (&offset_expr, "ldc1", "T,o(b)", treg, BFD_RELOC_MIPS_LITERAL, mips_gp_register); @@ -8951,8 +8954,7 @@ macro (struct mips_cl_insn *ip) macro_build_lui (&offset_expr, AT); } - if ((mips_opts.isa != ISA_MIPS1 || mips_opts.micromips) - && (mips_opts.arch != CPU_R5900)) + if (CPU_HAS_LDC1_SDC1 (mips_opts.arch) || mips_opts.micromips) { macro_build (&offset_expr, "ldc1", "T,o(b)", treg, BFD_RELOC_LO16, AT); @@ -8969,8 +8971,7 @@ macro (struct mips_cl_insn *ip) r = BFD_RELOC_LO16; dob: gas_assert (!mips_opts.micromips); - gas_assert ((mips_opts.isa == ISA_MIPS1) - || (mips_opts.arch == CPU_R5900)); + gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch)); macro_build (&offset_expr, "lwc1", "T,o(b)", target_big_endian ? treg + 1 : treg, r, breg); /* FIXME: A possible overflow which I don't know how to deal @@ -8982,7 +8983,7 @@ macro (struct mips_cl_insn *ip) case M_S_DOB: gas_assert (!mips_opts.micromips); - gas_assert (mips_opts.isa == ISA_MIPS1); + gas_assert (!CPU_HAS_LDC1_SDC1 (mips_opts.arch)); /* Even on a big endian machine $fn comes before $fn+1. We have to adjust when storing to memory. */ macro_build (&offset_expr, "swc1", "T,o(b)", @@ -9008,7 +9009,7 @@ macro (struct mips_cl_insn *ip) /* Itbl support may require additional care here. */ coproc = 1; fmt = "T,o(b)"; - if ((mips_opts.isa != ISA_MIPS1) && (mips_opts.arch != CPU_R5900)) + if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) { s = "ldc1"; goto ld_st; @@ -9021,7 +9022,7 @@ macro (struct mips_cl_insn *ip) /* Itbl support may require additional care here. */ coproc = 1; fmt = "T,o(b)"; - if ((mips_opts.isa != ISA_MIPS1) && (mips_opts.arch != CPU_R5900)) + if (CPU_HAS_LDC1_SDC1 (mips_opts.arch)) { s = "sdc1"; goto ld_st; @@ -9922,7 +9923,7 @@ macro (struct mips_cl_insn *ip) case M_TRUNCWS: case M_TRUNCWD: gas_assert (!mips_opts.micromips); - gas_assert ((mips_opts.isa == ISA_MIPS1) || (mips_opts.arch == CPU_R5900)); + gas_assert (mips_opts.isa == ISA_MIPS1); used_at = 1; sreg = (ip->insn_opcode >> 11) & 0x1f; /* floating reg */ dreg = (ip->insn_opcode >> 06) & 0x1f; /* floating reg */ |