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| author | Chris Demetriou <cgd@google.com> | 2001-10-24 21:08:34 +0000 |
|---|---|---|
| committer | Chris Demetriou <cgd@google.com> | 2001-10-24 21:08:34 +0000 |
| commit | 0a758a12213514ec64b95fcb325912e39d117fce (patch) | |
| tree | afd9e768454769cea0eeea0aa146b545dbc948d8 /gas/config/tc-mips.c | |
| parent | e4320fb31a49d49704d3b3d7a8d0934d5ef32cff (diff) | |
| download | gdb-0a758a12213514ec64b95fcb325912e39d117fce.zip gdb-0a758a12213514ec64b95fcb325912e39d117fce.tar.gz gdb-0a758a12213514ec64b95fcb325912e39d117fce.tar.bz2 | |
2001-10-24 Chris Demetriou <cgd@broadcom.com>
* config/tc-mips.c (hilo_interlocks, cop_interlocks): Make
these evaluate to true if mips_arch indicates SB-1.
Diffstat (limited to 'gas/config/tc-mips.c')
| -rw-r--r-- | gas/config/tc-mips.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 847ee2c..96f13a0 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -258,6 +258,7 @@ static int mips_fp32 = 0; require nops to be inserted. */ #define hilo_interlocks (mips_arch == CPU_R4010 \ + || mips_arch == CPU_SB1 \ ) /* Whether the processor uses hardware interlocks to protect reads @@ -270,6 +271,7 @@ static int mips_fp32 = 0; (co-processor) interlocks. */ /* Itbl support may require additional care here. */ #define cop_interlocks (mips_arch == CPU_R4300 \ + || mips_arch == CPU_SB1 \ ) /* Is this a mfhi or mflo instruction? */ |