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| author | Richard Sandiford <rdsandiford@googlemail.com> | 2007-07-04 19:55:18 +0000 |
|---|---|---|
| committer | Richard Sandiford <rdsandiford@googlemail.com> | 2007-07-04 19:55:18 +0000 |
| commit | 0fdf1951981eafd070b503e8dab596d7c9ad07a7 (patch) | |
| tree | 143ad53c6904d6a00fde2e6724f8ab2b08b05532 /gas/config/tc-mips.c | |
| parent | e600c1cf4e3a85c6b30e44e650b815e7b1524488 (diff) | |
| download | gdb-0fdf1951981eafd070b503e8dab596d7c9ad07a7.zip gdb-0fdf1951981eafd070b503e8dab596d7c9ad07a7.tar.gz gdb-0fdf1951981eafd070b503e8dab596d7c9ad07a7.tar.bz2 | |
gas/
* config/tc-mips.c (mips_cpu_info_table): Add new entries for
{24k,24ke,34k,74k}f{2_1,1_1,x}. Also add an entry for 74kf3_2.
Deprecate *x and *fx.
* doc/c-mips.texi: Document the new CPU arguments. Deprecate
*x and *fx.
Diffstat (limited to 'gas/config/tc-mips.c')
| -rw-r--r-- | gas/config/tc-mips.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 79114df..42626ab 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -14784,24 +14784,48 @@ static const struct mips_cpu_info mips_cpu_info_table[] = { "m4k", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, { "m4kp", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, { "24kc", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, + { "24kf2_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, { "24kf", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, + { "24kf1_1", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, + /* Deprecated forms of the above. */ + { "24kfx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, { "24kx", 0, ISA_MIPS32R2, CPU_MIPS32R2 }, /* 24KE is a 24K with DSP ASE, other ASEs are optional. */ { "24kec", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, + { "24kef2_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, { "24kef", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, + { "24kef1_1", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, + /* Deprecated forms of the above. */ + { "24kefx", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, { "24kex", MIPS_CPU_ASE_DSP, ISA_MIPS32R2, CPU_MIPS32R2 }, /* 34K is a 24K with DSP and MT ASE, other ASEs are optional. */ { "34kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, + { "34kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, + ISA_MIPS32R2, CPU_MIPS32R2 }, { "34kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, + { "34kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, + ISA_MIPS32R2, CPU_MIPS32R2 }, + /* Deprecated forms of the above. */ + { "34kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, + ISA_MIPS32R2, CPU_MIPS32R2 }, { "34kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_MT, ISA_MIPS32R2, CPU_MIPS32R2 }, /* 74K with DSP and DSPR2 ASE, other ASEs are optional. */ { "74kc", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, + { "74kf2_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, + ISA_MIPS32R2, CPU_MIPS32R2 }, { "74kf", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, + { "74kf1_1", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, + ISA_MIPS32R2, CPU_MIPS32R2 }, + { "74kf3_2", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, + ISA_MIPS32R2, CPU_MIPS32R2 }, + /* Deprecated forms of the above. */ + { "74kfx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, + ISA_MIPS32R2, CPU_MIPS32R2 }, { "74kx", MIPS_CPU_ASE_DSP | MIPS_CPU_ASE_DSPR2, ISA_MIPS32R2, CPU_MIPS32R2 }, |