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| author | Jim Wilson <wilson@tuliptree.org> | 2000-08-16 23:20:15 +0000 |
|---|---|---|
| committer | Jim Wilson <wilson@tuliptree.org> | 2000-08-16 23:20:15 +0000 |
| commit | 50b81f1903a517fd16ec7a266d6c4668a5e37cce (patch) | |
| tree | d2e1c065868c30785b3ead12e1620244dfaa3dbc /gas/config/tc-ia64.c | |
| parent | d670a150a1aa97f5b0a1e8e03184f7390a558310 (diff) | |
| download | gdb-50b81f1903a517fd16ec7a266d6c4668a5e37cce.zip gdb-50b81f1903a517fd16ec7a266d6c4668a5e37cce.tar.gz gdb-50b81f1903a517fd16ec7a266d6c4668a5e37cce.tar.bz2 | |
Fix 3 DV bugs, and a few minor cleanups.
gas/
* config/tc-ia64.c (specify_resource, case IA64_RS_GR): Handle
postincrement modified registers. Handle IA64_OPND_R3_2 addl
source registers.
(note_register_values): Handle IA64_OPND_R3_2 operands.
gas/testsuite/
* gas/ia64/dv-raw-err.s: Add new tests for addl and postinc.
* gas/ia64/dv-raw-err.l: Likewise.
* gas/ia64/dv-waw-err.l: Update sed pattern.
* gas/ia64/opc-f.pl: Delete fpsub, and fpadd comment.
* gas/ia64/opc-f.s, gas/ia64/opc-f.d: Regenerate.
include/opcode/
* ia64.h (IA64_OPCODE_POSTINC): New.
opcodes/
* ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds. Delete
break, mov-immediate, nop.
* ia64-opc-f.c: Delete fpsub instructions.
* ia64-opc-m.c: Add POSTINC to all instructions with postincrement
address operand. Rewrite using macros to avoid long lines.
* ia64-opc.h (POSTINC): Define.
* ia64-asmtab.c: Regenerate.
Diffstat (limited to 'gas/config/tc-ia64.c')
| -rw-r--r-- | gas/config/tc-ia64.c | 38 |
1 files changed, 26 insertions, 12 deletions
diff --git a/gas/config/tc-ia64.c b/gas/config/tc-ia64.c index 297b0da..66d63c7 100644 --- a/gas/config/tc-ia64.c +++ b/gas/config/tc-ia64.c @@ -6820,17 +6820,23 @@ dep->name, idesc->name, (rsrc_write?"write":"read"), note) { if (rsrc_write) { - for (i=0;i < idesc->num_outputs;i++) - { - if (idesc->operands[i] == IA64_OPND_R1 - || idesc->operands[i] == IA64_OPND_R2 - || idesc->operands[i] == IA64_OPND_R3) - { - specs[count] = tmpl; - specs[count++].index = - CURR_SLOT.opnd[i].X_add_number - REG_GR; - } - } + for (i= 0; i < idesc->num_outputs; i++) + if (idesc->operands[i] == IA64_OPND_R1 + || idesc->operands[i] == IA64_OPND_R2 + || idesc->operands[i] == IA64_OPND_R3) + { + specs[count] = tmpl; + specs[count++].index = + CURR_SLOT.opnd[i].X_add_number - REG_GR; + } + if (idesc->flags & IA64_OPCODE_POSTINC) + for (i = 0; i < NELEMS (idesc->operands); i++) + if (idesc->operands[i] == IA64_OPND_MR3) + { + specs[count] = tmpl; + specs[count++].index = + CURR_SLOT.opnd[i].X_add_number - REG_GR; + } } else { @@ -6849,7 +6855,9 @@ dep->name, idesc->name, (rsrc_write?"write":"read"), note) || ((i >= idesc->num_outputs) && (idesc->operands[i] == IA64_OPND_R1 || idesc->operands[i] == IA64_OPND_R2 - || idesc->operands[i] == IA64_OPND_R3))) + || idesc->operands[i] == IA64_OPND_R3 + /* addl source register. */ + || idesc->operands[i] == IA64_OPND_R3_2))) { specs[count] = tmpl; specs[count++].index = @@ -7681,6 +7689,12 @@ note_register_values (idesc) if (regno > 0 && regno < NELEMS(gr_values)) gr_values[regno].known = 0; } + else if (idesc->operands[i] == IA64_OPND_R3_2) + { + int regno = CURR_SLOT.opnd[i].X_add_number - REG_GR; + if (regno > 0 && regno < 4) + gr_values[regno].known = 0; + } else if (idesc->operands[i] == IA64_OPND_P1 || idesc->operands[i] == IA64_OPND_P2) { |