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| author | H.J. Lu <hjl.tools@gmail.com> | 2007-11-14 22:31:54 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2007-11-14 22:31:54 +0000 |
| commit | 4f8631b1d4f2b34021d2e4827a3d392684f3243d (patch) | |
| tree | 8cdf13f448702ed652ca12cc7677a581c1f45228 /gas/config/tc-ia64.c | |
| parent | 07f397aba39f619db4fdce42c9e91cb07dd4dc68 (diff) | |
| download | gdb-4f8631b1d4f2b34021d2e4827a3d392684f3243d.zip gdb-4f8631b1d4f2b34021d2e4827a3d392684f3243d.tar.gz gdb-4f8631b1d4f2b34021d2e4827a3d392684f3243d.tar.bz2 | |
gas/
2007-11-14 Tristan Gingold <gingold@adacore.com>
* config/tc-ia64.c (AR_RUC): Defined.
(ar): Add "ar.ruc".
(specify_resource): Handle AR_RUC like AR_ITC.
gas/testsuite/
2007-11-14 H.J. Lu <hongjiu.lu@intel.com>
* gas/ia64/dv-raw-err.s: Add tests for ar.ruc.
* gas/ia64/dv-waw-err.s: Likewise.
* gas/ia64/invalid-ar.s: Likewise.
* gas/ia64/regs.s: Add tests for ar.ruc and ar44.
* gas/ia64/dv-raw-err.l: Updated.
* gas/ia64/dv-waw-err.l: Likewise.
* gas/ia64/invalid-ar.l: Likewise.
* gas/ia64/regs.d: Likewise.
opcodes/
2007-11-14 H.J. Lu <hongjiu.lu@intel.com>
* ia64-ic.tbl: Updated for Itanium 9100 series.
* ia64-raw.tbl: Likewise.
* ia64-waw.tbl: Likewise.
* ia64-asmtab.c: Regenerated.
2007-11-14 Tristan Gingold <gingold@adacore.com>
* ia64-dis.c (print_insn_ia64): Handle ar.ruc.
* ia64-gen.c (lookup_regindex): Likewise.
Diffstat (limited to 'gas/config/tc-ia64.c')
| -rw-r--r-- | gas/config/tc-ia64.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/gas/config/tc-ia64.c b/gas/config/tc-ia64.c index 92c8ea9..2e0f86c 100644 --- a/gas/config/tc-ia64.c +++ b/gas/config/tc-ia64.c @@ -366,6 +366,7 @@ static unsigned char le_nop_stop[16] = #define AR_UNAT 36 #define AR_FPSR 40 #define AR_ITC 44 +#define AR_RUC 45 #define AR_PFS 64 #define AR_LC 65 #define AR_EC 66 @@ -389,8 +390,8 @@ ar[] = {"ar.fir", AR_FIR}, {"ar.fdr", AR_FDR}, {"ar.ccv", AR_CCV}, {"ar.unat", AR_UNAT}, {"ar.fpsr", AR_FPSR}, {"ar.itc", AR_ITC}, - {"ar.pfs", AR_PFS}, {"ar.lc", AR_LC}, - {"ar.ec", AR_EC}, + {"ar.ruc", AR_RUC}, {"ar.pfs", AR_PFS}, + {"ar.lc", AR_LC}, {"ar.ec", AR_EC}, }; /* control registers: */ @@ -9256,9 +9257,9 @@ dep->name, idesc->name, (rsrc_write?"write":"read"), note) CURR_SLOT.opnd[index].X_add_number - REG_AR; if (regno == AR_ITC + || regno == AR_RUC || (index == 0 - && (regno == AR_ITC - || regno == AR_RSC + && (regno == AR_RSC || (regno >= AR_K0 && regno <= AR_K7)))) { |