Convert unmaintained files over to ISO-C90 and fix formatting.

1 files changed, 1441 insertions, 1822 deletions

diff --git a/gas/config/tc-i960.c b/gas/config/tc-i960.c
index 1786afe..8d4c303 100644
--- a/gas/config/tc-i960.c
+++ b/gas/config/tc-i960.c
@@ -74,32 +74,32 @@
 
 #if defined (OBJ_AOUT) || defined (OBJ_BOUT)
 
-#define TC_S_IS_SYSPROC(s)	((1<=S_GET_OTHER(s)) && (S_GET_OTHER(s)<=32))
-#define TC_S_IS_BALNAME(s)	(S_GET_OTHER(s) == N_BALNAME)
-#define TC_S_IS_CALLNAME(s)	(S_GET_OTHER(s) == N_CALLNAME)
-#define TC_S_IS_BADPROC(s)	((S_GET_OTHER(s) != 0) && !TC_S_IS_CALLNAME(s) && !TC_S_IS_BALNAME(s) && !TC_S_IS_SYSPROC(s))
+#define TC_S_IS_SYSPROC(s)	((1 <= S_GET_OTHER (s)) && (S_GET_OTHER (s) <= 32))
+#define TC_S_IS_BALNAME(s)	(S_GET_OTHER (s) == N_BALNAME)
+#define TC_S_IS_CALLNAME(s)	(S_GET_OTHER (s) == N_CALLNAME)
+#define TC_S_IS_BADPROC(s)	((S_GET_OTHER (s) != 0) && !TC_S_IS_CALLNAME (s) && !TC_S_IS_BALNAME (s) && !TC_S_IS_SYSPROC (s))
 
-#define TC_S_SET_SYSPROC(s, p)	(S_SET_OTHER((s), (p)+1))
-#define TC_S_GET_SYSPROC(s)	(S_GET_OTHER(s)-1)
+#define TC_S_SET_SYSPROC(s, p)	(S_SET_OTHER ((s), (p) + 1))
+#define TC_S_GET_SYSPROC(s)	(S_GET_OTHER (s) - 1)
 
-#define TC_S_FORCE_TO_BALNAME(s)	(S_SET_OTHER((s), N_BALNAME))
-#define TC_S_FORCE_TO_CALLNAME(s)	(S_SET_OTHER((s), N_CALLNAME))
+#define TC_S_FORCE_TO_BALNAME(s)	(S_SET_OTHER ((s), N_BALNAME))
+#define TC_S_FORCE_TO_CALLNAME(s)	(S_SET_OTHER ((s), N_CALLNAME))
 #define TC_S_FORCE_TO_SYSPROC(s)	{;}
 
 #else /* ! OBJ_A/BOUT */
 #ifdef OBJ_COFF
 
-#define TC_S_IS_SYSPROC(s)	(S_GET_STORAGE_CLASS(s) == C_SCALL)
-#define TC_S_IS_BALNAME(s)	(SF_GET_BALNAME(s))
-#define TC_S_IS_CALLNAME(s)	(SF_GET_CALLNAME(s))
-#define TC_S_IS_BADPROC(s)	(TC_S_IS_SYSPROC(s) && TC_S_GET_SYSPROC(s) < 0 && 31 < TC_S_GET_SYSPROC(s))
+#define TC_S_IS_SYSPROC(s)	(S_GET_STORAGE_CLASS (s) == C_SCALL)
+#define TC_S_IS_BALNAME(s)	(SF_GET_BALNAME (s))
+#define TC_S_IS_CALLNAME(s)	(SF_GET_CALLNAME (s))
+#define TC_S_IS_BADPROC(s)	(TC_S_IS_SYSPROC (s) && TC_S_GET_SYSPROC (s) < 0 && 31 < TC_S_GET_SYSPROC (s))
 
 #define TC_S_SET_SYSPROC(s, p)	((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx = (p))
 #define TC_S_GET_SYSPROC(s)	((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx)
 
-#define TC_S_FORCE_TO_BALNAME(s)	(SF_SET_BALNAME(s))
-#define TC_S_FORCE_TO_CALLNAME(s)	(SF_SET_CALLNAME(s))
-#define TC_S_FORCE_TO_SYSPROC(s)	(S_SET_STORAGE_CLASS((s), C_SCALL))
+#define TC_S_FORCE_TO_BALNAME(s)	(SF_SET_BALNAME (s))
+#define TC_S_FORCE_TO_CALLNAME(s)	(SF_SET_CALLNAME (s))
+#define TC_S_FORCE_TO_SYSPROC(s)	(S_SET_STORAGE_CLASS ((s), C_SCALL))
 
 #else /* ! OBJ_COFF */
 #ifdef OBJ_ELF
@@ -110,7 +110,7 @@
 #define TC_S_IS_BADPROC(s)	0
 
 #define TC_S_SET_SYSPROC(s, p)
-#define TC_S_GET_SYSPROC(s) 0
+#define TC_S_GET_SYSPROC(s)     0
 
 #define TC_S_FORCE_TO_BALNAME(s)
 #define TC_S_FORCE_TO_CALLNAME(s)
@@ -135,64 +135,12 @@ const int md_reloc_size = sizeof (struct relocation_info);
 struct memS;
 struct regop;
 
-/* Emit branch-prediction instrumentation code */
-static void brcnt_emit PARAMS ((void));
-/* Return next branch local label */
-static char *brlab_next PARAMS ((void));
-/* Generate COBR instruction */
-static void cobr_fmt PARAMS ((char *[], long, struct i960_opcode *));
-/* Generate CTRL instruction */
-static void ctrl_fmt PARAMS ((char *, long, int));
-/* Emit (internally) binary */
-static char *emit PARAMS ((long));
-/* Break arguments out of comma-separated list */
-static int get_args PARAMS ((char *, char *[]));
-/* Handle COBR or CTRL displacement */
-static void get_cdisp PARAMS ((char *, char *, long, int, int, int));
-/* Find index specification string */
-static char *get_ispec PARAMS ((char *));
-/* Translate text to register number */
-static int get_regnum PARAMS ((char *));
-/* Lexical scan of instruction source */
-static int i_scan PARAMS ((char *, char *[]));
-/* Generate MEMA or MEMB instruction */
-static void mem_fmt PARAMS ((char *[], struct i960_opcode *, int));
-/* Convert MEMA instruction to MEMB format */
-static void mema_to_memb PARAMS ((char *));
-/* Parse an expression */
-static void parse_expr PARAMS ((char *, expressionS *));
-/* Parse and replace a 'ldconst' pseudo-op */
-static int parse_ldconst PARAMS ((char *[]));
-/* Parse a memory operand */
-static void parse_memop PARAMS ((struct memS *, char *, int));
-/* Parse machine-dependent pseudo-op */
-static void parse_po PARAMS ((int));
-/* Parse a register operand */
-static void parse_regop PARAMS ((struct regop *, char *, char));
-/* Generate a REG format instruction */
-static void reg_fmt PARAMS ((char *[], struct i960_opcode *));
-/* "De-optimize" cobr into compare/branch */
-static void relax_cobr PARAMS ((fragS *));
-/* Process '.leafproc' pseudo-op */
-static void s_leafproc PARAMS ((int, char *[]));
-/* Process '.sysproc' pseudo-op */
-static void s_sysproc PARAMS ((int, char *[]));
-/* Will a 'shlo' substitute for a 'ldconst'? */
-static int shift_ok PARAMS ((int));
-/* Give syntax error */
-static void syntax PARAMS ((void));
-/* Target chip supports spec-func register? */
-static int targ_has_sfr PARAMS ((int));
-/* Target chip supports instruction set? */
-static int targ_has_iclass PARAMS ((int));
-
-/* See md_parse_option() for meanings of these options */
-static char norelax;		/* True if -norelax switch seen */
-static char instrument_branches;	/* True if -b switch seen */
+/* See md_parse_option() for meanings of these options.  */
+static char norelax;			/* True if -norelax switch seen.  */
+static char instrument_branches;	/* True if -b switch seen.  */
 
 /* Characters that always start a comment.
-   If the pre-processor is disabled, these aren't very useful.
- */
+   If the pre-processor is disabled, these aren't very useful.  */
 const char comment_chars[] = "#";
 
 /* Characters that only start a comment at the beginning of
@@ -201,21 +149,18 @@ const char comment_chars[] = "#";
 
    Note that input_file.c hand checks for '#' at the beginning of the
    first line of the input file.  This is because the compiler outputs
-   #NO_APP at the beginning of its output.
- */
+   #NO_APP at the beginning of its output.  */
 
 /* Also note that comments started like this one will always work.  */
 
-const char line_comment_chars[] = "#";
-
+const char line_comment_chars[]   = "#";
 const char line_separator_chars[] = ";";
 
-/* Chars that can be used to separate mant from exp in floating point nums */
+/* Chars that can be used to separate mant from exp in floating point nums.  */
 const char EXP_CHARS[] = "eE";
 
 /* Chars that mean this number is a floating point constant,
-   as in 0f12.456 or 0d1.2345e12
- */
+   as in 0f12.456 or 0d1.2345e12.  */
 const char FLT_CHARS[] = "fFdDtT";
 
 /* Table used by base assembler to relax addresses based on varying length
@@ -227,52 +172,34 @@ const char FLT_CHARS[] = "fFdDtT";
 
    For i80960, the only application is the (de-)optimization of cobr
    instructions into separate compare and branch instructions when a 13-bit
-   displacement won't hack it.
- */
+   displacement won't hack it.  */
 const relax_typeS md_relax_table[] =
 {
-  {0, 0, 0, 0},			/* State 0 => no more relaxation possible */
-  {4088, -4096, 0, 2},		/* State 1: conditional branch (cobr) */
-  {0x800000 - 8, -0x800000, 4, 0},	/* State 2: compare (reg) & branch (ctrl) */
+  {0, 0, 0, 0},				/* State 0 => no more relaxation possible.  */
+  {4088, -4096, 0, 2},			/* State 1: conditional branch (cobr).  */
+  {0x800000 - 8, -0x800000, 4, 0},	/* State 2: compare (reg) & branch (ctrl).  */
 };
 
-static void s_endian PARAMS ((int));
-
 /* These are the machine dependent pseudo-ops.
 
    This table describes all the machine specific pseudo-ops the assembler
    has to support.  The fields are:
         pseudo-op name without dot
         function to call to execute this pseudo-op
-        integer arg to pass to the function
- */
+        integer arg to pass to the function.  */
 #define S_LEAFPROC	1
 #define S_SYSPROC	2
 
-const pseudo_typeS md_pseudo_table[] =
-{
-  {"bss", s_lcomm, 1},
-  {"endian", s_endian, 0},
-  {"extended", float_cons, 't'},
-  {"leafproc", parse_po, S_LEAFPROC},
-  {"sysproc", parse_po, S_SYSPROC},
-
-  {"word", cons, 4},
-  {"quad", cons, 16},
-
-  {0, 0, 0}
-};
-
-/* Macros to extract info from an 'expressionS' structure 'e' */
+/* Macros to extract info from an 'expressionS' structure 'e'.  */
 #define adds(e)	e.X_add_symbol
 #define offs(e)	e.X_add_number
 
-/* Branch-prediction bits for CTRL/COBR format opcodes */
-#define BP_MASK		0x00000002	/* Mask for branch-prediction bit */
-#define BP_TAKEN	0x00000000	/* Value to OR in to predict branch */
-#define BP_NOT_TAKEN	0x00000002	/* Value to OR in to predict no branch */
+/* Branch-prediction bits for CTRL/COBR format opcodes.  */
+#define BP_MASK		0x00000002	/* Mask for branch-prediction bit.  */
+#define BP_TAKEN	0x00000000	/* Value to OR in to predict branch.  */
+#define BP_NOT_TAKEN	0x00000002	/* Value to OR in to predict no branch.  */
 
-/* Some instruction opcodes that we need explicitly */
+/* Some instruction opcodes that we need explicitly.  */
 #define BE	0x12000000
 #define BG	0x11000000
 #define BGE	0x13000000
@@ -301,12 +228,12 @@ const pseudo_typeS md_pseudo_table[] =
    used).  */
 #define MEMA_ABASE	0x2000
 
-/* Info from which a MEMA or MEMB format instruction can be generated */
+/* Info from which a MEMA or MEMB format instruction can be generated.  */
 typedef struct memS
   {
-    /* (First) 32 bits of instruction */
+    /* (First) 32 bits of instruction.  */
     long opcode;
-    /* 0-(none), 12- or, 32-bit displacement needed */
+    /* 0-(none), 12- or, 32-bit displacement needed.  */
     int disp;
     /* The expression in the source instruction from which the
        displacement should be determined.  */
@@ -314,12 +241,12 @@ typedef struct memS
   }
 memS;
 
-/* The two pieces of info we need to generate a register operand */
+/* The two pieces of info we need to generate a register operand.  */
 struct regop
   {
-    int mode;			/* 0 =>local/global/spec reg; 1=> literal or fp reg */
-    int special;		/* 0 =>not a sfr;  1=> is a sfr (not valid w/mode=0) */
-    int n;			/* Register number or literal value */
+    int mode;			/* 0 =>local/global/spec reg; 1=> literal or fp reg.  */
+    int special;		/* 0 =>not a sfr;  1=> is a sfr (not valid w/mode=0).  */
+    int n;			/* Register number or literal value.  */
   };
 
 /* Number and assembler mnemonic for all registers that can appear in
@@ -420,10 +347,10 @@ regnames[] =
 /* Number and assembler mnemonic for all registers that can appear as
    'abase' (indirect addressing) registers.  */
 static const struct
-  {
-    char *areg_name;
-    int areg_num;
-  }
+{
+  char *areg_name;
+  int areg_num;
+}
 aregs[] =
 {
   { "(pfp)", 0 },
@@ -467,24 +394,23 @@ aregs[] =
   { NULL, 0 },				/* END OF LIST */
 };
 
-/* Hash tables */
-static struct hash_control *op_hash;	/* Opcode mnemonics */
-static struct hash_control *reg_hash;	/* Register name hash table */
-static struct hash_control *areg_hash;	/* Abase register hash table */
+/* Hash tables.  */
+static struct hash_control *op_hash;	/* Opcode mnemonics.  */
+static struct hash_control *reg_hash;	/* Register name hash table.  */
+static struct hash_control *areg_hash;	/* Abase register hash table.  */
 
-/* Architecture for which we are assembling */
-#define ARCH_ANY	0	/* Default: no architecture checking done */
+/* Architecture for which we are assembling.  */
+#define ARCH_ANY	0	/* Default: no architecture checking done.  */
 #define ARCH_KA		1
 #define ARCH_KB		2
 #define ARCH_MC		3
 #define ARCH_CA		4
 #define ARCH_JX		5
 #define ARCH_HX		6
-int architecture = ARCH_ANY;	/* Architecture requested on invocation line */
+int architecture = ARCH_ANY;	/* Architecture requested on invocation line.  */
 int iclasses_seen;		/* OR of instruction classes (I_* constants)
-				 *    for which we've actually assembled
-				 *      instructions.
-				 */
+				      for which we've actually assembled
+				        instructions.  */
 
 /* BRANCH-PREDICTION INSTRUMENTATION
 
@@ -519,8 +445,7 @@ int iclasses_seen;		/* OR of instruction classes (I_* constants)
 
             Note that input source code is expected to already contain calls
             an external routine that will link the branch local table into a
-            list of such tables.
- */
+            list of such tables.  */
 
 /* Number of branches instrumented so far.  Also used to generate
    unique local labels for each instrumented branch.  */
@@ -537,19 +462,16 @@ static int br_cnt;
 #define BR_TAB_NAME	"__BRANCH_TABLE__"
 /* Name of the table of pointers to branches.  A local (i.e.,
    non-external) symbol.  */
-
-/*****************************************************************************
-   md_begin:  One-time initialization.
 
-  	Set up hash tables.
+static void ctrl_fmt (char *, long, int);
 
-  *************************************************************************** */
+
 void
-md_begin ()
+md_begin (void)
 {
-  int i;			/* Loop counter */
-  const struct i960_opcode *oP;	/* Pointer into opcode table */
-  const char *retval;		/* Value returned by hash functions */
+  int i;			/* Loop counter.  */
+  const struct i960_opcode *oP;	/* Pointer into opcode table.  */
+  const char *retval;		/* Value returned by hash functions.  */
 
   op_hash = hash_new ();
   reg_hash = hash_new ();
@@ -560,7 +482,7 @@ md_begin ()
   retval = 0;
 
   for (oP = i960_opcodes; oP->name && !retval; oP++)
-    retval = hash_insert (op_hash, oP->name, (PTR) oP);
+    retval = hash_insert (op_hash, oP->name, (void *) oP);
 
   for (i = 0; regnames[i].reg_name && !retval; i++)
     retval = hash_insert (reg_hash, regnames[i].reg_name,
@@ -574,904 +496,92 @@ md_begin ()
     as_fatal (_("Hashing returned \"%s\"."), retval);
 }
 
-/*****************************************************************************
-   md_assemble:  Assemble an instruction
-
-   Assumptions about the passed-in text:
-  	- all comments, labels removed
-  	- text is an instruction
-  	- all white space compressed to single blanks
-  	- all character constants have been replaced with decimal
-
-  *************************************************************************** */
-void
-md_assemble (textP)
-     char *textP;		/* Source text of instruction */
-{
-  /* Parsed instruction text, containing NO whitespace: arg[0]->opcode
-     mnemonic arg[1-3]->operands, with char constants replaced by
-     decimal numbers.  */
-  char *args[4];
-
-  int n_ops;			/* Number of instruction operands */
-  /* Pointer to instruction description */
-  struct i960_opcode *oP;
-  /* TRUE iff opcode mnemonic included branch-prediction suffix (".f"
-     or ".t").  */
-  int branch_predict;
-  /* Setting of branch-prediction bit(s) to be OR'd into instruction
-     opcode of CTRL/COBR format instructions.  */
-  long bp_bits;
-
-  int n;			/* Offset of last character in opcode mnemonic */
-
-  const char *bp_error_msg = _("branch prediction invalid on this opcode");
-
-  /* Parse instruction into opcode and operands */
-  memset (args, '\0', sizeof (args));
-  n_ops = i_scan (textP, args);
-  if (n_ops == -1)
-    {
-      return;			/* Error message already issued */
-    }
-
-  /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction */
-  if (!strcmp (args[0], "ldconst"))
-    {
-      n_ops = parse_ldconst (args);
-      if (n_ops == -1)
-	{
-	  return;
-	}
-    }
-
-  /* Check for branch-prediction suffix on opcode mnemonic, strip it off */
-  n = strlen (args[0]) - 1;
-  branch_predict = 0;
-  bp_bits = 0;
-  if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f'))
-    {
-      /* We could check here to see if the target architecture
-	 supports branch prediction, but why bother?  The bit will
-	 just be ignored by processors that don't use it.  */
-      branch_predict = 1;
-      bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN;
-      args[0][n - 1] = '\0';	/* Strip suffix from opcode mnemonic */
-    }
-
-  /* Look up opcode mnemonic in table and check number of operands.
-     Check that opcode is legal for the target architecture.  If all
-     looks good, assemble instruction.  */
-  oP = (struct i960_opcode *) hash_find (op_hash, args[0]);
-  if (!oP || !targ_has_iclass (oP->iclass))
-    {
-      as_bad (_("invalid opcode, \"%s\"."), args[0]);
-
-    }
-  else if (n_ops != oP->num_ops)
-    {
-      as_bad (_("improper number of operands.  expecting %d, got %d"),
-	      oP->num_ops, n_ops);
-    }
-  else
-    {
-      switch (oP->format)
-	{
-	case FBRA:
-	case CTRL:
-	  ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops);
-	  if (oP->format == FBRA)
-	    {
-	      /* Now generate a 'bno' to same arg */
-	      ctrl_fmt (args[1], BNO | bp_bits, 1);
-	    }
-	  break;
-	case COBR:
-	case COJ:
-	  cobr_fmt (args, oP->opcode | bp_bits, oP);
-	  break;
-	case REG:
-	  if (branch_predict)
-	    {
-	      as_warn (bp_error_msg);
-	    }
-	  reg_fmt (args, oP);
-	  break;
-	case MEM1:
-	  if (args[0][0] == 'c' && args[0][1] == 'a')
-	    {
-	      if (branch_predict)
-		{
-		  as_warn (bp_error_msg);
-		}
-	      mem_fmt (args, oP, 1);
-	      break;
-	    }
-	case MEM2:
-	case MEM4:
-	case MEM8:
-	case MEM12:
-	case MEM16:
-	  if (branch_predict)
-	    {
-	      as_warn (bp_error_msg);
-	    }
-	  mem_fmt (args, oP, 0);
-	  break;
-	case CALLJ:
-	  if (branch_predict)
-	    {
-	      as_warn (bp_error_msg);
-	    }
-	  /* Output opcode & set up "fixup" (relocation); flag
-	     relocation as 'callj' type.  */
-	  know (oP->num_ops == 1);
-	  get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1);
-	  break;
-	default:
-	  BAD_CASE (oP->format);
-	  break;
-	}
-    }
-}				/* md_assemble() */
-
-/*****************************************************************************
-   md_number_to_chars:  convert a number to target byte order
-
-  *************************************************************************** */
-void
-md_number_to_chars (buf, value, n)
-     char *buf;
-     valueT value;
-     int n;
-{
-  number_to_chars_littleendian (buf, value, n);
-}
-
-/*****************************************************************************
-   md_chars_to_number:  convert from target byte order to host byte order.
-
-  *************************************************************************** */
-static int md_chars_to_number PARAMS ((char *, int));
-
-static int
-md_chars_to_number (val, n)
-     char *val;			/* Value in target byte order */
-     int n;			/* Number of bytes in the input */
-{
-  int retval;
+/* parse_expr:		parse an expression
 
-  for (retval = 0; n--;)
-    {
-      retval <<= 8;
-      retval |= (unsigned char) val[n];
-    }
-  return retval;
-}
+   Use base assembler's expression parser to parse an expression.
+   It, unfortunately, runs off a global which we have to save/restore
+   in order to make it work for us.
 
-#define MAX_LITTLENUMS	6
-#define LNUM_SIZE	sizeof (LITTLENUM_TYPE)
+   An empty expression string is treated as an absolute 0.
 
-/*****************************************************************************
-   md_atof:	convert ascii to floating point
-
-   Turn a string at input_line_pointer into a floating point constant of type
-   'type', and store the appropriate bytes at *litP.  The number of LITTLENUMS
-   emitted is returned at 'sizeP'.  An error message is returned, or a pointer
-   to an empty message if OK.
-
-   Note we call the i386 floating point routine, rather than complicating
-   things with more files or symbolic links.
-
-  *************************************************************************** */
-char *
-md_atof (type, litP, sizeP)
-     int type;
-     char *litP;
-     int *sizeP;
-{
-  LITTLENUM_TYPE words[MAX_LITTLENUMS];
-  LITTLENUM_TYPE *wordP;
-  int prec;
-  char *t;
-
-  switch (type)
-    {
-    case 'f':
-    case 'F':
-      prec = 2;
-      break;
-
-    case 'd':
-    case 'D':
-      prec = 4;
-      break;
-
-    case 't':
-    case 'T':
-      prec = 5;
-      type = 'x';		/* That's what atof_ieee() understands */
-      break;
-
-    default:
-      *sizeP = 0;
-      return _("Bad call to md_atof()");
-    }
-
-  t = atof_ieee (input_line_pointer, type, words);
-  if (t)
-    {
-      input_line_pointer = t;
-    }
-
-  *sizeP = prec * LNUM_SIZE;
-
-  /* Output the LITTLENUMs in REVERSE order in accord with i80960
-     word-order.  (Dunno why atof_ieee doesn't do it in the right
-     order in the first place -- probably because it's a hack of
-     atof_m68k.)  */
-
-  for (wordP = words + prec - 1; prec--;)
-    {
-      md_number_to_chars (litP, (long) (*wordP--), LNUM_SIZE);
-      litP += sizeof (LITTLENUM_TYPE);
-    }
-
-  return 0;
-}
-
-/*****************************************************************************
-   md_number_to_imm
-
-  *************************************************************************** */
-static void md_number_to_imm PARAMS ((char *, long, int));
-
-static void
-md_number_to_imm (buf, val, n)
-     char *buf;
-     long val;
-     int n;
-{
-  md_number_to_chars (buf, val, n);
-}
-
-/*****************************************************************************
-   md_number_to_field:
-
-  	Stick a value (an address fixup) into a bit field of
-  	previously-generated instruction.
-
-  *************************************************************************** */
-static void md_number_to_field PARAMS ((char *, long, bit_fixS *));
+   Sets O_illegal regardless of expression evaluation if entire input
+   string is not consumed in the evaluation -- tolerate no dangling junk!  */
 
 static void
-md_number_to_field (instrP, val, bfixP)
-     char *instrP;		/* Pointer to instruction to be fixed */
-     long val;			/* Address fixup value */
-     bit_fixS *bfixP;		/* Description of bit field to be fixed up */
+parse_expr (char *textP,		/* Text of expression to be parsed.  */
+	    expressionS *expP)		/* Where to put the results of parsing.  */
 {
-  int numbits;			/* Length of bit field to be fixed */
-  long instr;			/* 32-bit instruction to be fixed-up */
-  long sign;			/* 0 or -1, according to sign bit of 'val' */
-
-  /* Convert instruction back to host byte order.  */
-  instr = md_chars_to_number (instrP, 4);
-
-  /* Surprise! -- we stored the number of bits to be modified rather
-     than a pointer to a structure.  */
-  numbits = (int) (size_t) bfixP;
-  if (numbits == 1)
-    {
-      /* This is a no-op, stuck here by reloc_callj() */
-      return;
-    }
-
-  know ((numbits == 13) || (numbits == 24));
-
-  /* Propagate sign bit of 'val' for the given number of bits.  Result
-     should be all 0 or all 1.  */
-  sign = val >> ((int) numbits - 1);
-  if (((val < 0) && (sign != -1))
-      || ((val > 0) && (sign != 0)))
-    {
-      as_bad (_("Fixup of %ld too large for field width of %d"),
-	      val, numbits);
-    }
-  else
-    {
-      /* Put bit field into instruction and write back in target
-         * byte order.
-       */
-      val &= ~(-1 << (int) numbits);	/* Clear unused sign bits */
-      instr |= val;
-      md_number_to_chars (instrP, instr, 4);
-    }
-}				/* md_number_to_field() */
-
-
-/*****************************************************************************
-   md_parse_option
-  	Invocation line includes a switch not recognized by the base assembler.
-  	See if it's a processor-specific option.  For the 960, these are:
-
-  	-norelax:
-  		Conditional branch instructions that require displacements
-  		greater than 13 bits (or that have external targets) should
-  		generate errors.  The default is to replace each such
-  		instruction with the corresponding compare (or chkbit) and
-  		branch instructions.  Note that the Intel "j" cobr directives
-  		are ALWAYS "de-optimized" in this way when necessary,
-  		regardless of the setting of this option.
-
-  	-b:
-  		Add code to collect information about branches taken, for
-  		later optimization of branch prediction bits by a separate
-  		tool.  COBR and CNTL format instructions have branch
-  		prediction bits (in the CX architecture);  if "BR" represents
-  		an instruction in one of these classes, the following rep-
-  		resents the code generated by the assembler:
-
-  			call	<increment routine>
-  			.word	0	# pre-counter
-  		Label:  BR
-  			call	<increment routine>
-  			.word	0	# post-counter
-
-  		A table of all such "Labels" is also generated.
-
-  	-AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
-  		Select the 80960 architecture.  Instructions or features not
-  		supported by the selected architecture cause fatal errors.
-  		The default is to generate code for any instruction or feature
-  		that is supported by SOME version of the 960 (even if this
-  		means mixing architectures!).
-
-  ****************************************************************************/
-
-const char *md_shortopts = "A:b";
-struct option md_longopts[] =
-{
-#define OPTION_LINKRELAX (OPTION_MD_BASE)
-  {"linkrelax", no_argument, NULL, OPTION_LINKRELAX},
-  {"link-relax", no_argument, NULL, OPTION_LINKRELAX},
-#define OPTION_NORELAX (OPTION_MD_BASE + 1)
-  {"norelax", no_argument, NULL, OPTION_NORELAX},
-  {"no-relax", no_argument, NULL, OPTION_NORELAX},
-  {NULL, no_argument, NULL, 0}
-};
-size_t md_longopts_size = sizeof (md_longopts);
-
-struct tabentry
-  {
-    char *flag;
-    int arch;
-  };
-static const struct tabentry arch_tab[] =
-{
-  {"KA", ARCH_KA},
-  {"KB", ARCH_KB},
-  {"SA", ARCH_KA},		/* Synonym for KA */
-  {"SB", ARCH_KB},		/* Synonym for KB */
-  {"KC", ARCH_MC},		/* Synonym for MC */
-  {"MC", ARCH_MC},
-  {"CA", ARCH_CA},
-  {"JX", ARCH_JX},
-  {"HX", ARCH_HX},
-  {NULL, 0}
-};
-
-int
-md_parse_option (c, arg)
-     int c;
-     char *arg;
-{
-  switch (c)
-    {
-    case OPTION_LINKRELAX:
-      linkrelax = 1;
-      flag_keep_locals = 1;
-      break;
-
-    case OPTION_NORELAX:
-      norelax = 1;
-      break;
-
-    case 'b':
-      instrument_branches = 1;
-      break;
-
-    case 'A':
-      {
-	const struct tabentry *tp;
-	char *p = arg;
-
-	for (tp = arch_tab; tp->flag != NULL; tp++)
-	  if (!strcmp (p, tp->flag))
-	    break;
-
-	if (tp->flag == NULL)
-	  {
-	    as_bad (_("invalid architecture %s"), p);
-	    return 0;
-	  }
-	else
-	  architecture = tp->arch;
-      }
-      break;
-
-    default:
-      return 0;
-    }
-
-  return 1;
-}
-
-void
-md_show_usage (stream)
-     FILE *stream;
-{
-  int i;
-  fprintf (stream, _("I960 options:\n"));
-  for (i = 0; arch_tab[i].flag; i++)
-    fprintf (stream, "%s-A%s", i ? " | " : "", arch_tab[i].flag);
-  fprintf (stream, _("\n\
-			specify variant of 960 architecture\n\
--b			add code to collect statistics about branches taken\n\
--link-relax		preserve individual alignment directives so linker\n\
-			can do relaxing (b.out format only)\n\
--no-relax		don't alter compare-and-branch instructions for\n\
-			long displacements\n"));
-}
-
-
-/*****************************************************************************
-   md_convert_frag:
-  	Called by base assembler after address relaxation is finished:  modify
-  	variable fragments according to how much relaxation was done.
-
-  	If the fragment substate is still 1, a 13-bit displacement was enough
-  	to reach the symbol in question.  Set up an address fixup, but otherwise
-  	leave the cobr instruction alone.
-
-  	If the fragment substate is 2, a 13-bit displacement was not enough.
-  	Replace the cobr with a two instructions (a compare and a branch).
-
-  *************************************************************************** */
-#ifndef BFD_ASSEMBLER
-void
-md_convert_frag (headers, seg, fragP)
-     object_headers *headers ATTRIBUTE_UNUSED;
-     segT seg ATTRIBUTE_UNUSED;
-     fragS *fragP;
-#else
-void
-md_convert_frag (abfd, sec, fragP)
-     bfd *abfd ATTRIBUTE_UNUSED;
-     segT sec ATTRIBUTE_UNUSED;
-     fragS *fragP;
-#endif
-{
-  fixS *fixP;			/* Structure describing needed address fix */
-
-  switch (fragP->fr_subtype)
-    {
-    case 1:
-      /* LEAVE SINGLE COBR INSTRUCTION */
-      fixP = fix_new (fragP,
-		      fragP->fr_opcode - fragP->fr_literal,
-		      4,
-		      fragP->fr_symbol,
-		      fragP->fr_offset,
-		      1,
-		      NO_RELOC);
-
-      fixP->fx_bit_fixP = (bit_fixS *) 13;	/* size of bit field */
-      break;
-    case 2:
-      /* REPLACE COBR WITH COMPARE/BRANCH INSTRUCTIONS */
-      relax_cobr (fragP);
-      break;
-    default:
-      BAD_CASE (fragP->fr_subtype);
-      break;
-    }
-}
-
-/*****************************************************************************
-   md_estimate_size_before_relax:  How much does it look like *fragP will grow?
-
-  	Called by base assembler just before address relaxation.
-  	Return the amount by which the fragment will grow.
-
-  	Any symbol that is now undefined will not become defined; cobr's
-  	based on undefined symbols will have to be replaced with a compare
-  	instruction and a branch instruction, and the code fragment will grow
-  	by 4 bytes.
-
-  *************************************************************************** */
-int
-md_estimate_size_before_relax (fragP, segment_type)
-     register fragS *fragP;
-     register segT segment_type;
-{
-  /* If symbol is undefined in this segment, go to "relaxed" state
-     (compare and branch instructions instead of cobr) right now.  */
-  if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type)
-    {
-      relax_cobr (fragP);
-      return 4;
-    }
-
-  return md_relax_table[fragP->fr_subtype].rlx_length;
-}				/* md_estimate_size_before_relax() */
-
-#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
-
-/*****************************************************************************
-   md_ri_to_chars:
-  	This routine exists in order to overcome machine byte-order problems
-  	when dealing with bit-field entries in the relocation_info struct.
-
-  	But relocation info will be used on the host machine only (only
-  	executable code is actually downloaded to the i80960).  Therefore,
-  	we leave it in host byte order.
-
-  *************************************************************************** */
-static void md_ri_to_chars PARAMS ((char *, struct relocation_info *));
-
-static void
-md_ri_to_chars (where, ri)
-     char *where;
-     struct relocation_info *ri;
-{
-  host_number_to_chars (where, ri->r_address, 4);
-  host_number_to_chars (where + 4, ri->r_index, 3);
-#if WORDS_BIGENDIAN
-  where[7] = (ri->r_pcrel << 7
-	      | ri->r_length << 5
-	      | ri->r_extern << 4
-	      | ri->r_bsr << 3
-	      | ri->r_disp << 2
-	      | ri->r_callj << 1
-	      | ri->nuthin << 0);
-#else
-  where[7] = (ri->r_pcrel << 0
-	      | ri->r_length << 1
-	      | ri->r_extern << 3
-	      | ri->r_bsr << 4
-	      | ri->r_disp << 5
-	      | ri->r_callj << 6
-	      | ri->nuthin << 7);
-#endif
-}
-
-#endif /* defined(OBJ_AOUT) | defined(OBJ_BOUT) */
-
-
-/* FOLLOWING ARE THE LOCAL ROUTINES, IN ALPHABETICAL ORDER  */
-
-/*****************************************************************************
-   brcnt_emit:	Emit code to increment inline branch counter.
-
-  	See the comments above the declaration of 'br_cnt' for details on
-  	branch-prediction instrumentation.
-  *************************************************************************** */
-static void
-brcnt_emit ()
-{
-  ctrl_fmt (BR_CNT_FUNC, CALL, 1);	/* Emit call to "increment" routine */
-  emit (0);			/* Emit inline counter to be incremented */
-}
-
-/*****************************************************************************
-   brlab_next:	generate the next branch local label
-
-  	See the comments above the declaration of 'br_cnt' for details on
-  	branch-prediction instrumentation.
-  *************************************************************************** */
-static char *
-brlab_next ()
-{
-  static char buf[20];
-
-  sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++);
-  return buf;
-}
-
-/*****************************************************************************
-   brtab_emit:	generate the fetch-prediction branch table.
-
-  	See the comments above the declaration of 'br_cnt' for details on
-  	branch-prediction instrumentation.
-
-  	The code emitted here would be functionally equivalent to the following
-  	example assembler source.
-
-  			.data
-  			.align	2
-  	   BR_TAB_NAME:
-  			.word	0		# link to next table
-  			.word	3		# length of table
-  			.word	LBRANCH0	# 1st entry in table proper
-  			.word	LBRANCH1
-  			.word	LBRANCH2
-  **************************************************************************** */
-void
-brtab_emit ()
-{
-  int i;
-  char buf[20];
-  char *p;			/* Where the binary was output to */
-  /* Pointer to description of deferred address fixup.  */
-  fixS *fixP;
-
-  if (!instrument_branches)
-    {
-      return;
-    }
-
-  subseg_set (data_section, 0);	/*      .data */
-  frag_align (2, 0, 0);		/*      .align 2 */
-  record_alignment (now_seg, 2);
-  colon (BR_TAB_NAME);		/* BR_TAB_NAME: */
-  emit (0);			/*      .word 0 #link to next table */
-  emit (br_cnt);		/*      .word n #length of table */
-
-  for (i = 0; i < br_cnt; i++)
-    {
-      sprintf (buf, "%s%d", BR_LABEL_BASE, i);
-      p = emit (0);
-      fixP = fix_new (frag_now,
-		      p - frag_now->fr_literal,
-		      4,
-		      symbol_find (buf),
-		      0,
-		      0,
-		      NO_RELOC);
-    }
-}
-
-/*****************************************************************************
-   cobr_fmt:	generate a COBR-format instruction
-
-  *************************************************************************** */
-static void
-cobr_fmt (arg, opcode, oP)
-     /* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */
-     char *arg[];
-     /* Opcode, with branch-prediction bits already set if necessary.  */
-     long opcode;
-     /* Pointer to description of instruction.  */
-     struct i960_opcode *oP;
-{
-  long instr;			/* 32-bit instruction */
-  struct regop regop;		/* Description of register operand */
-  int n;			/* Number of operands */
-  int var_frag;			/* 1 if varying length code fragment should
-				 *    be emitted;  0 if an address fix
-				 *      should be emitted.
-				 */
-
-  instr = opcode;
-  n = oP->num_ops;
-
-  if (n >= 1)
-    {
-      /* First operand (if any) of a COBR is always a register
-	 operand.  Parse it.  */
-      parse_regop (&regop, arg[1], oP->operand[0]);
-      instr |= (regop.n << 19) | (regop.mode << 13);
-    }
-  if (n >= 2)
-    {
-      /* Second operand (if any) of a COBR is always a register
-	 operand.  Parse it.  */
-    parse_regop (&regop, arg[2], oP->operand[1]);
-      instr |= (regop.n << 14) | regop.special;
-    }
-
-  if (n < 3)
-    {
-      emit (instr);
-
-    }
-  else
-    {
-      if (instrument_branches)
-	{
-	  brcnt_emit ();
-	  colon (brlab_next ());
-	}
-
-      /* A third operand to a COBR is always a displacement.  Parse
-         it; if it's relaxable (a cobr "j" directive, or any cobr
-         other than bbs/bbc when the "-norelax" option is not in use)
-         set up a variable code fragment; otherwise set up an address
-         fix.  */
-      var_frag = !norelax || (oP->format == COJ);	/* TRUE or FALSE */
-      get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0);
-
-      if (instrument_branches)
-	{
-	  brcnt_emit ();
-	}
-    }
-}				/* cobr_fmt() */
-
-/*****************************************************************************
-   ctrl_fmt:	generate a CTRL-format instruction
+  char *save_in;		/* Save global here.  */
+  symbolS *symP;
 
-  *************************************************************************** */
-static void
-ctrl_fmt (targP, opcode, num_ops)
-     char *targP;		/* Pointer to text of lone operand (if any) */
-     long opcode;		/* Template of instruction */
-     int num_ops;		/* Number of operands */
-{
-  int instrument;		/* TRUE iff we should add instrumentation to track
-				   * how often the branch is taken
-				 */
+  know (textP);
 
-  if (num_ops == 0)
+  if (*textP == '\0')
     {
-      emit (opcode);		/* Output opcode */
+      /* Treat empty string as absolute 0.  */
+      expP->X_add_symbol = expP->X_op_symbol = NULL;
+      expP->X_add_number = 0;
+      expP->X_op = O_constant;
     }
   else
     {
+      save_in = input_line_pointer;	/* Save global.  */
+      input_line_pointer = textP;	/* Make parser work for us.  */
 
-      instrument = instrument_branches && (opcode != CALL)
-	&& (opcode != B) && (opcode != RET) && (opcode != BAL);
-
-      if (instrument)
-	{
-	  brcnt_emit ();
-	  colon (brlab_next ());
-	}
+      (void) expression (expP);
+      if ((size_t) (input_line_pointer - textP) != strlen (textP))
+	/* Did not consume all of the input.  */
+	expP->X_op = O_illegal;
 
-      /* The operand MUST be an ip-relative displacement. Parse it
-         * and set up address fix for the instruction we just output.
-       */
-      get_cdisp (targP, "CTRL", opcode, 24, 0, 0);
+      symP = expP->X_add_symbol;
+      if (symP && (hash_find (reg_hash, S_GET_NAME (symP))))
+	/* Register name in an expression.  */
+	/* FIXME: this isn't much of a check any more.  */
+	expP->X_op = O_illegal;
 
-      if (instrument)
-	{
-	  brcnt_emit ();
-	}
+      input_line_pointer = save_in;	/* Restore global.  */
     }
-
 }
 
-/*****************************************************************************
-   emit:	output instruction binary
+/* emit:	output instruction binary
 
-  	Output instruction binary, in target byte order, 4 bytes at a time.
-  	Return pointer to where it was placed.
+   Output instruction binary, in target byte order, 4 bytes at a time.
+   Return pointer to where it was placed.  */
 
-  *************************************************************************** */
 static char *
-emit (instr)
-     long instr;		/* Word to be output, host byte order */
+emit (long instr)		/* Word to be output, host byte order.  */
 {
-  char *toP;			/* Where to output it */
+  char *toP;			/* Where to output it.  */
 
-  toP = frag_more (4);		/* Allocate storage */
-  md_number_to_chars (toP, instr, 4);	/* Convert to target byte order */
+  toP = frag_more (4);		/* Allocate storage.  */
+  md_number_to_chars (toP, instr, 4);	/* Convert to target byte order.  */
   return toP;
 }
 
-/*****************************************************************************
-   get_args:	break individual arguments out of comma-separated list
-
-   Input assumptions:
-  	- all comments and labels have been removed
-  	- all strings of whitespace have been collapsed to a single blank.
-  	- all character constants ('x') have been replaced with decimal
-
-   Output:
-  	args[0] is untouched. args[1] points to first operand, etc. All args:
-  	- are NULL-terminated
-  	- contain no whitespace
-
-   Return value:
-  	Number of operands (0,1,2, or 3) or -1 on error.
-
-  *************************************************************************** */
-static int
-get_args (p, args)
-     /* Pointer to comma-separated operands; MUCKED BY US */
-     register char *p;
-     /* Output arg: pointers to operands placed in args[1-3].  MUST
-        ACCOMMODATE 4 ENTRIES (args[0-3]).  */
-     char *args[];
-{
-  register int n;		/* Number of operands */
-  register char *to;
-
-  /* Skip lead white space */
-  while (*p == ' ')
-    {
-      p++;
-    }
-
-  if (*p == '\0')
-    {
-      return 0;
-    }
-
-  n = 1;
-  args[1] = p;
-
-  /* Squeze blanks out by moving non-blanks toward start of string.
-     * Isolate operands, whenever comma is found.
-   */
-  to = p;
-  while (*p != '\0')
-    {
-
-      if (*p == ' '
-	  && (! ISALNUM (p[1])
-	      || ! ISALNUM (p[-1])))
-	{
-	  p++;
-
-	}
-      else if (*p == ',')
-	{
-
-	  /* Start of operand */
-	  if (n == 3)
-	    {
-	      as_bad (_("too many operands"));
-	      return -1;
-	    }
-	  *to++ = '\0';		/* Terminate argument */
-	  args[++n] = to;	/* Start next argument */
-	  p++;
-
-	}
-      else
-	{
-	  *to++ = *p++;
-	}
-    }
-  *to = '\0';
-  return n;
-}
-
-/*****************************************************************************
-   get_cdisp:	handle displacement for a COBR or CTRL instruction.
+/* get_cdisp:	handle displacement for a COBR or CTRL instruction.
 
-  	Parse displacement for a COBR or CTRL instruction.
+   Parse displacement for a COBR or CTRL instruction.
 
-  	If successful, output the instruction opcode and set up for it,
-  	depending on the arg 'var_frag', either:
+   If successful, output the instruction opcode and set up for it,
+   depending on the arg 'var_frag', either:
   	    o an address fixup to be done when all symbol values are known, or
   	    o a varying length code fragment, with address fixup info.  This
   		will be done for cobr instructions that may have to be relaxed
   		in to compare/branch instructions (8 bytes) if the final
-  		address displacement is greater than 13 bits.
+  		address displacement is greater than 13 bits.  */
 
-  ****************************************************************************/
 static void
-get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
-     /* displacement as specified in source instruction */
-     char *dispP;
-     /* "COBR" or "CTRL" (for use in error message) */
-     char *ifmtP;
-     /* Instruction needing the displacement */
-     long instr;
-     /* # bits of displacement (13 for COBR, 24 for CTRL) */
-     int numbits;
-     /* 1 if varying length code fragment should be emitted;
-      *       0 if an address fix should be emitted.
-      */
-     int var_frag;
-     /* 1 if callj relocation should be done; else 0 */
-     int callj;
-{
-  expressionS e;		/* Parsed expression */
-  fixS *fixP;			/* Structure describing needed address fix */
-  char *outP;			/* Where instruction binary is output to */
+get_cdisp (char *dispP, /* Displacement as specified in source instruction.  */
+	   char *ifmtP, /* "COBR" or "CTRL" (for use in error message).  */
+	   long instr,  /* Instruction needing the displacement.  */
+	   int numbits, /* # bits of displacement (13 for COBR, 24 for CTRL).  */
+	   int var_frag,/* 1 if varying length code fragment should be emitted;
+			   0 if an address fix should be emitted.  */
+	   int callj)	/* 1 if callj relocation should be done; else 0.  */	   
+{
+  expressionS e;		/* Parsed expression.  */
+  fixS *fixP;			/* Structure describing needed address fix.  */
+  char *outP;			/* Where instruction binary is output to.  */
 
   fixP = NULL;
 
@@ -1487,7 +597,7 @@ get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
 	{
 	  if (var_frag)
 	    {
-	      outP = frag_more (8);	/* Allocate worst-case storage */
+	      outP = frag_more (8);	/* Allocate worst-case storage.  */
 	      md_number_to_chars (outP, instr, 4);
 	      frag_variant (rs_machine_dependent, 4, 4, 1,
 			    adds (e), offs (e), outP);
@@ -1495,8 +605,7 @@ get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
 	  else
 	    {
 	      /* Set up a new fix structure, so address can be updated
-	       * when all symbol values are known.
-	       */
+	         when all symbol values are known.  */
 	      outP = emit (instr);
 	      fixP = fix_new (frag_now,
 			      outP - frag_now->fr_literal,
@@ -1509,10 +618,9 @@ get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
 	      fixP->fx_tcbit = callj;
 
 	      /* We want to modify a bit field when the address is
-	       * known.  But we don't need all the garbage in the
-	       * bit_fix structure.  So we're going to lie and store
-	       * the number of bits affected instead of a pointer.
-	       */
+	         known.  But we don't need all the garbage in the
+	         bit_fix structure.  So we're going to lie and store
+	         the number of bits affected instead of a pointer.  */
 	      fixP->fx_bit_fixP = (bit_fixS *) (size_t) numbits;
 	    }
 	}
@@ -1526,67 +634,75 @@ get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
     }
 }
 
-/*****************************************************************************
-   get_ispec:	parse a memory operand for an index specification
+static int
+md_chars_to_number (char * val,		/* Value in target byte order.  */
+		    int n)		/* Number of bytes in the input.  */
+{
+  int retval;
 
-  	Here, an "index specification" is taken to be anything surrounded
-  	by square brackets and NOT followed by anything else.
+  for (retval = 0; n--;)
+    {
+      retval <<= 8;
+      retval |= (unsigned char) val[n];
+    }
+  return retval;
+}
 
-  	If it's found, detach it from the input string, remove the surrounding
-  	square brackets, and return a pointer to it.  Otherwise, return NULL.
+/* mema_to_memb:	convert a MEMA-format opcode to a MEMB-format opcode.
 
-  *************************************************************************** */
-static char *
-get_ispec (textP)
-     /* Pointer to memory operand from source instruction, no white space.  */
-     char *textP;
+   There are 2 possible MEMA formats:
+  	- displacement only
+  	- displacement + abase
+
+   They are distinguished by the setting of the MEMA_ABASE bit.  */
+
+static void
+mema_to_memb (char * opcodeP)	/* Where to find the opcode, in target byte order.  */
 {
-  /* Points to start of index specification.  */
-  char *start;
-  /* Points to end of index specification.  */
-  char *end;
+  long opcode;			/* Opcode in host byte order.  */
+  long mode;			/* Mode bits for MEMB instruction.  */
 
-  /* Find opening square bracket, if any.  */
-  start = strchr (textP, '[');
+  opcode = md_chars_to_number (opcodeP, 4);
+  know (!(opcode & MEMB_BIT));
 
-  if (start != NULL)
-    {
+  mode = MEMB_BIT | D_BIT;
+  if (opcode & MEMA_ABASE)
+    mode |= A_BIT;
 
-      /* Eliminate '[', detach from rest of operand */
-      *start++ = '\0';
+  opcode &= 0xffffc000;		/* Clear MEMA offset and mode bits.  */
+  opcode |= mode;		/* Set MEMB mode bits.  */
 
-      end = strchr (start, ']');
+  md_number_to_chars (opcodeP, opcode, 4);
+}
 
-      if (end == NULL)
-	{
-	  as_bad (_("unmatched '['"));
+/* targ_has_sfr:
 
-	}
-      else
-	{
-	  /* Eliminate ']' and make sure it was the last thing
-	     * in the string.
-	   */
-	  *end = '\0';
-	  if (*(end + 1) != '\0')
-	    {
-	      as_bad (_("garbage after index spec ignored"));
-	    }
-	}
+   Return TRUE iff the target architecture supports the specified
+   special-function register (sfr).  */
+
+static int
+targ_has_sfr (int n)		/* Number (0-31) of sfr.  */
+{
+  switch (architecture)
+    {
+    case ARCH_KA:
+    case ARCH_KB:
+    case ARCH_MC:
+    case ARCH_JX:
+      return 0;
+    case ARCH_HX:
+      return ((0 <= n) && (n <= 4));
+    case ARCH_CA:
+    default:
+      return ((0 <= n) && (n <= 2));
     }
-  return start;
 }
 
-/*****************************************************************************
-   get_regnum:
+/* Look up a (suspected) register name in the register table and return the
+   associated register number (or -1 if not found).  */
 
-  	Look up a (suspected) register name in the register table and return the
-  	associated register number (or -1 if not found).
-
-  *************************************************************************** */
 static int
-get_regnum (regname)
-     char *regname;		/* Suspected register name */
+get_regnum (char *regname)	/* Suspected register name.  */
 {
   int *rP;
 
@@ -1594,358 +710,152 @@ get_regnum (regname)
   return (rP == NULL) ? -1 : *rP;
 }
 
-/*****************************************************************************
-   i_scan:	perform lexical scan of ascii assembler instruction.
-
-   Input assumptions:
-  	- input string is an i80960 instruction (not a pseudo-op)
-  	- all comments and labels have been removed
-  	- all strings of whitespace have been collapsed to a single blank.
-
-   Output:
-  	args[0] points to opcode, other entries point to operands. All strings:
-  	- are NULL-terminated
-  	- contain no whitespace
-  	- have character constants ('x') replaced with a decimal number
-
-   Return value:
-  	Number of operands (0,1,2, or 3) or -1 on error.
+/* syntax: Issue a syntax error.  */
 
-  *************************************************************************** */
-static int
-i_scan (iP, args)
-     /* Pointer to ascii instruction;  MUCKED BY US.  */
-     register char *iP;
-     /* Output arg: pointers to opcode and operands placed here.  MUST
-	ACCOMMODATE 4 ENTRIES.  */
-     char *args[];
+static void
+syntax (void)
 {
+  as_bad (_("syntax error"));
+}
 
-  /* Isolate opcode */
-  if (*(iP) == ' ')
-    {
-      iP++;
-    }				/* Skip lead space, if any */
-  args[0] = iP;
-  for (; *iP != ' '; iP++)
-    {
-      if (*iP == '\0')
-	{
-	  /* There are no operands */
-	  if (args[0] == iP)
-	    {
-	      /* We never moved: there was no opcode either! */
-	      as_bad (_("missing opcode"));
-	      return -1;
-	    }
-	  return 0;
-	}
-    }
-  *iP++ = '\0';			/* Terminate opcode */
-  return (get_args (iP, args));
-}				/* i_scan() */
+/* parse_regop: parse a register operand.
 
-/*****************************************************************************
-   mem_fmt:	generate a MEMA- or MEMB-format instruction
+   In case of illegal operand, issue a message and return some valid
+   information so instruction processing can continue.  */
 
-  *************************************************************************** */
 static void
-mem_fmt (args, oP, callx)
-     char *args[];		/* args[0]->opcode mnemonic, args[1-3]->operands */
-     struct i960_opcode *oP;	/* Pointer to description of instruction */
-     int callx;			/* Is this a callx opcode */
-{
-  int i;			/* Loop counter */
-  struct regop regop;		/* Description of register operand */
-  char opdesc;			/* Operand descriptor byte */
-  memS instr;			/* Description of binary to be output */
-  char *outP;			/* Where the binary was output to */
-  expressionS expr;		/* Parsed expression */
-  /* ->description of deferred address fixup */
-  fixS *fixP;
-
-#ifdef OBJ_COFF
-  /* COFF support isn't in place yet for callx relaxing.  */
-  callx = 0;
-#endif
-
-  memset (&instr, '\0', sizeof (memS));
-  instr.opcode = oP->opcode;
+parse_regop (struct regop *regopP,	/* Where to put description of register operand.  */
+	     char *optext,		/* Text of operand.  */
+	     char opdesc)      		/* Descriptor byte:  what's legal for this operand.  */
+{
+  int n;			/* Register number.  */
+  expressionS e;		/* Parsed expression.  */
 
-  /* Process operands.  */
-  for (i = 1; i <= oP->num_ops; i++)
+  /* See if operand is a register.  */
+  n = get_regnum (optext);
+  if (n >= 0)
     {
-      opdesc = oP->operand[i - 1];
-
-      if (MEMOP (opdesc))
+      if (IS_RG_REG (n))
 	{
-	  parse_memop (&instr, args[i], oP->format);
+	  /* Global or local register.  */
+	  if (!REG_ALIGN (opdesc, n))
+	    as_bad (_("unaligned register"));
+
+	  regopP->n = n;
+	  regopP->mode = 0;
+	  regopP->special = 0;
+	  return;
 	}
-      else
+      else if (IS_FP_REG (n) && FP_OK (opdesc))
 	{
-	  parse_regop (&regop, args[i], opdesc);
-	  instr.opcode |= regop.n << 19;
+	  /* Floating point register, and it's allowed.  */
+	  regopP->n = n - FP0;
+	  regopP->mode = 1;
+	  regopP->special = 0;
+	  return;
 	}
-    }
-
-  /* Parse the displacement; this must be done before emitting the
-     opcode, in case it is an expression using `.'.  */
-  parse_expr (instr.e, &expr);
-
-  /* Output opcode */
-  outP = emit (instr.opcode);
+      else if (IS_SF_REG (n) && SFR_OK (opdesc))
+	{
+	  /* Special-function register, and it's allowed.  */
+	  regopP->n = n - SF0;
+	  regopP->mode = 0;
+	  regopP->special = 1;
+	  if (!targ_has_sfr (regopP->n))
+	    as_bad (_("no such sfr in this architecture"));
 
-  if (instr.disp == 0)
-    {
-      return;
+	  return;
+	}
     }
-
-  /* Process the displacement */
-  switch (expr.X_op)
+  else if (LIT_OK (opdesc))
     {
-    case O_illegal:
-      as_bad (_("expression syntax error"));
-      break;
-
-    case O_constant:
-      if (instr.disp == 32)
-	{
-	  (void) emit (offs (expr));	/* Output displacement */
-	}
-      else
+      /* How about a literal?  */
+      regopP->mode = 1;
+      regopP->special = 0;
+      if (FP_OK (opdesc))
 	{
-	  /* 12-bit displacement */
-	  if (offs (expr) & ~0xfff)
+	  /* Floating point literal acceptable.  */
+	  /* Skip over 0f, 0d, or 0e prefix.  */
+	  if ((optext[0] == '0')
+	      && (optext[1] >= 'd')
+	      && (optext[1] <= 'f'))
+	    optext += 2;
+
+	  if (!strcmp (optext, "0.0") || !strcmp (optext, "0"))
 	    {
-	      /* Won't fit in 12 bits: convert already-output
-	       * instruction to MEMB format, output
-	       * displacement.
-	       */
-	      mema_to_memb (outP);
-	      (void) emit (offs (expr));
+	      regopP->n = 0x10;
+	      return;
 	    }
-	  else
+
+	  if (!strcmp (optext, "1.0") || !strcmp (optext, "1"))
 	    {
-	      /* WILL fit in 12 bits:  OR into opcode and
-	       * overwrite the binary we already put out
-	       */
-	      instr.opcode |= offs (expr);
-	      md_number_to_chars (outP, instr.opcode, 4);
+	      regopP->n = 0x16;
+	      return;
 	    }
 	}
-      break;
-
-    default:
-      if (instr.disp == 12)
+      else
 	{
-	  /* Displacement is dependent on a symbol, whose value
-	   * may change at link time.  We HAVE to reserve 32 bits.
-	   * Convert already-output opcode to MEMB format.
-	   */
-	  mema_to_memb (outP);
+	  /* Fixed point literal acceptable.  */
+	  parse_expr (optext, &e);
+	  if (e.X_op != O_constant
+	      || (offs (e) < 0) || (offs (e) > 31))
+	    {
+	      as_bad (_("illegal literal"));
+	      offs (e) = 0;
+	    }
+	  regopP->n = offs (e);
+	  return;
 	}
-
-      /* Output 0 displacement and set up address fixup for when
-       * this symbol's value becomes known.
-       */
-      outP = emit ((long) 0);
-      fixP = fix_new_exp (frag_now,
-			  outP - frag_now->fr_literal,
-			  4,
-			  &expr,
-			  0,
-			  NO_RELOC);
-      /* Steve's linker relaxing hack.  Mark this 32-bit relocation as
-         being in the instruction stream, specifically as part of a callx
-         instruction.  */
-      fixP->fx_bsr = callx;
-      break;
     }
-}				/* memfmt() */
-
-/*****************************************************************************
-   mema_to_memb:	convert a MEMA-format opcode to a MEMB-format opcode.
-
-   There are 2 possible MEMA formats:
-  	- displacement only
-  	- displacement + abase
-
-   They are distinguished by the setting of the MEMA_ABASE bit.
-
-  *************************************************************************** */
-static void
-mema_to_memb (opcodeP)
-     char *opcodeP;		/* Where to find the opcode, in target byte order */
-{
-  long opcode;			/* Opcode in host byte order */
-  long mode;			/* Mode bits for MEMB instruction */
 
-  opcode = md_chars_to_number (opcodeP, 4);
-  know (!(opcode & MEMB_BIT));
-
-  mode = MEMB_BIT | D_BIT;
-  if (opcode & MEMA_ABASE)
-    {
-      mode |= A_BIT;
-    }
-
-  opcode &= 0xffffc000;		/* Clear MEMA offset and mode bits */
-  opcode |= mode;		/* Set MEMB mode bits */
-
-  md_number_to_chars (opcodeP, opcode, 4);
-}				/* mema_to_memb() */
-
-/*****************************************************************************
-   parse_expr:		parse an expression
-
-  	Use base assembler's expression parser to parse an expression.
-  	It, unfortunately, runs off a global which we have to save/restore
-  	in order to make it work for us.
-
-  	An empty expression string is treated as an absolute 0.
-
-  	Sets O_illegal regardless of expression evaluation if entire input
-  	string is not consumed in the evaluation -- tolerate no dangling junk!
-
-  *************************************************************************** */
-static void
-parse_expr (textP, expP)
-     char *textP;		/* Text of expression to be parsed */
-     expressionS *expP;		/* Where to put the results of parsing */
-{
-  char *save_in;		/* Save global here */
-  symbolS *symP;
-
-  know (textP);
-
-  if (*textP == '\0')
-    {
-      /* Treat empty string as absolute 0 */
-      expP->X_add_symbol = expP->X_op_symbol = NULL;
-      expP->X_add_number = 0;
-      expP->X_op = O_constant;
-    }
-  else
-    {
-      save_in = input_line_pointer;	/* Save global */
-      input_line_pointer = textP;	/* Make parser work for us */
-
-      (void) expression (expP);
-      if ((size_t) (input_line_pointer - textP) != strlen (textP))
-	{
-	  /* Did not consume all of the input */
-	  expP->X_op = O_illegal;
-	}
-      symP = expP->X_add_symbol;
-      if (symP && (hash_find (reg_hash, S_GET_NAME (symP))))
-	{
-	  /* Register name in an expression */
-	  /* FIXME: this isn't much of a check any more.  */
-	  expP->X_op = O_illegal;
-	}
-
-      input_line_pointer = save_in;	/* Restore global */
-    }
+  /* Nothing worked.  */
+  syntax ();
+  regopP->mode = 0;		/* Register r0 is always a good one.  */
+  regopP->n = 0;
+  regopP->special = 0;
 }
 
-/*****************************************************************************
-   parse_ldcont:
-  	Parse and replace a 'ldconst' pseudo-instruction with an appropriate
-  	i80960 instruction.
-
-  	Assumes the input consists of:
-  		arg[0]	opcode mnemonic ('ldconst')
-  		arg[1]  first operand (constant)
-  		arg[2]	name of register to be loaded
-
-  	Replaces opcode and/or operands as appropriate.
+/* get_ispec:	parse a memory operand for an index specification
+   
+   Here, an "index specification" is taken to be anything surrounded
+   by square brackets and NOT followed by anything else.
 
-  	Returns the new number of arguments, or -1 on failure.
+   If it's found, detach it from the input string, remove the surrounding
+   square brackets, and return a pointer to it.  Otherwise, return NULL.  */
 
-  *************************************************************************** */
-static int
-parse_ldconst (arg)
-     char *arg[];		/* See above */
+static char *
+get_ispec (char *textP)  /* Pointer to memory operand from source instruction, no white space.  */
+	   
 {
-  int n;			/* Constant to be loaded */
-  int shift;			/* Shift count for "shlo" instruction */
-  static char buf[5];		/* Literal for first operand */
-  static char buf2[5];		/* Literal for second operand */
-  expressionS e;		/* Parsed expression */
+  /* Points to start of index specification.  */
+  char *start;
+  /* Points to end of index specification.  */
+  char *end;
 
-  arg[3] = NULL;		/* So we can tell at the end if it got used or not */
+  /* Find opening square bracket, if any.  */
+  start = strchr (textP, '[');
 
-  parse_expr (arg[1], &e);
-  switch (e.X_op)
+  if (start != NULL)
     {
-    default:
-      /* We're dependent on one or more symbols -- use "lda" */
-      arg[0] = "lda";
-      break;
-
-    case O_constant:
-      /* Try the following mappings:
-       *      ldconst 0,<reg>  ->mov  0,<reg>
-       *        ldconst 31,<reg> ->mov  31,<reg>
-       *        ldconst 32,<reg> ->addo 1,31,<reg>
-       *        ldconst 62,<reg> ->addo 31,31,<reg>
-       *        ldconst 64,<reg> ->shlo 8,3,<reg>
-       *        ldconst -1,<reg> ->subo 1,0,<reg>
-       *        ldconst -31,<reg>->subo 31,0,<reg>
-       *
-       * anything else becomes:
-       *        lda xxx,<reg>
-       */
-      n = offs (e);
-      if ((0 <= n) && (n <= 31))
-	{
-	  arg[0] = "mov";
-
-	}
-      else if ((-31 <= n) && (n <= -1))
-	{
-	  arg[0] = "subo";
-	  arg[3] = arg[2];
-	  sprintf (buf, "%d", -n);
-	  arg[1] = buf;
-	  arg[2] = "0";
-
-	}
-      else if ((32 <= n) && (n <= 62))
-	{
-	  arg[0] = "addo";
-	  arg[3] = arg[2];
-	  arg[1] = "31";
-	  sprintf (buf, "%d", n - 31);
-	  arg[2] = buf;
+      /* Eliminate '[', detach from rest of operand.  */
+      *start++ = '\0';
 
-	}
-      else if ((shift = shift_ok (n)) != 0)
-	{
-	  arg[0] = "shlo";
-	  arg[3] = arg[2];
-	  sprintf (buf, "%d", shift);
-	  arg[1] = buf;
-	  sprintf (buf2, "%d", n >> shift);
-	  arg[2] = buf2;
+      end = strchr (start, ']');
 
-	}
+      if (end == NULL)
+	as_bad (_("unmatched '['"));
       else
 	{
-	  arg[0] = "lda";
+	  /* Eliminate ']' and make sure it was the last thing
+	     in the string.  */
+	  *end = '\0';
+	  if (*(end + 1) != '\0')
+	    as_bad (_("garbage after index spec ignored"));
 	}
-      break;
-
-    case O_illegal:
-      as_bad (_("invalid constant"));
-      return -1;
-      break;
     }
-  return (arg[3] == 0) ? 2 : 3;
+  return start;
 }
 
-/*****************************************************************************
-   parse_memop:	parse a memory operand
+/* parse_memop:	parse a memory operand
 
   	This routine is based on the observation that the 4 mode bits of the
   	MEMB format, taken individually, have fairly consistent meaning:
@@ -1972,24 +882,22 @@ parse_ldconst (arg)
 
   	The other thing to observe is that we parse from the right, peeling
   	things * off as we go:  first any index spec, then any abase, then
-  	the displacement.
+  	the displacement.  */
 
-  *************************************************************************** */
 static void
-parse_memop (memP, argP, optype)
-     memS *memP;		/* Where to put the results */
-     char *argP;		/* Text of the operand to be parsed */
-     int optype;		/* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16 */
-{
-  char *indexP;			/* Pointer to index specification with "[]" removed */
-  char *p;			/* Temp char pointer */
-  char iprel_flag;		/* True if this is an IP-relative operand */
-  int regnum;			/* Register number */
+parse_memop (memS *memP,	/* Where to put the results.  */
+	     char *argP,	/* Text of the operand to be parsed.  */
+	     int optype)	/* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16.  */
+{
+  char *indexP;			/* Pointer to index specification with "[]" removed.  */
+  char *p;			/* Temp char pointer.  */
+  char iprel_flag;		/* True if this is an IP-relative operand.  */
+  int regnum;			/* Register number.  */
   /* Scale factor: 1,2,4,8, or 16.  Later converted to internal format
      (0,1,2,3,4 respectively).  */
   int scale;
-  int mode;			/* MEMB mode bits */
-  int *intP;			/* Pointer to register number */
+  int mode;			/* MEMB mode bits.  */
+  int *intP;			/* Pointer to register number.  */
 
   /* The following table contains the default scale factors for each
      type of memory instruction.  It is accessed using (optype-MEM1)
@@ -2028,21 +936,14 @@ parse_memop (memP, argP, optype)
 	  *p++ = '\0';		/* Eliminate '*' */
 
 	  /* Now indexP->a '\0'-terminated register name,
-	     * and p->a scale factor.
-	   */
+	     and p->a scale factor.  */
 
 	  if (!strcmp (p, "16"))
-	    {
-	      scale = 16;
-	    }
+	    scale = 16;
 	  else if (strchr ("1248", *p) && (p[1] == '\0'))
-	    {
-	      scale = *p - '0';
-	    }
+	    scale = *p - '0';
 	  else
-	    {
-	      scale = -1;
-	    }
+	    scale = -1;
 	}
 
       regnum = get_regnum (indexP);	/* Get index reg. # */
@@ -2052,7 +953,7 @@ parse_memop (memP, argP, optype)
 	  return;
 	}
 
-      /* Convert scale to its binary encoding */
+      /* Convert scale to its binary encoding.  */
       switch (scale)
 	{
 	case 1:
@@ -2075,11 +976,11 @@ parse_memop (memP, argP, optype)
 	  return;
 	};
 
-      memP->opcode |= scale | regnum;	/* Set index bits in opcode */
-      mode |= I_BIT;		/* Found a valid index spec */
+      memP->opcode |= scale | regnum;	/* Set index bits in opcode.  */
+      mode |= I_BIT;			/* Found a valid index spec.  */
     }
 
-  /* Any abase (Register Indirect) specification present? */
+  /* Any abase (Register Indirect) specification present?  */
   if ((p = strrchr (argP, '(')) != NULL)
     {
       /* "(" is there -- does it start a legal abase spec?  If not, it
@@ -2087,14 +988,12 @@ parse_memop (memP, argP, optype)
       intP = (int *) hash_find (areg_hash, p);
       if (intP != NULL)
 	{
-	  /* Got an abase here */
+	  /* Got an abase here.  */
 	  regnum = *intP;
-	  *p = '\0';		/* discard register spec */
+	  *p = '\0';		/* Discard register spec.  */
 	  if (regnum == IPREL)
-	    {
-	      /* We have to specialcase ip-rel mode */
-	      iprel_flag = 1;
-	    }
+	    /* We have to specialcase ip-rel mode.  */
+	    iprel_flag = 1;
 	  else
 	    {
 	      memP->opcode |= regnum << 14;
@@ -2103,29 +1002,25 @@ parse_memop (memP, argP, optype)
 	}
     }
 
-  /* Any expression present? */
+  /* Any expression present?  */
   memP->e = argP;
   if (*argP != '\0')
-    {
-      mode |= D_BIT;
-    }
+    mode |= D_BIT;
 
-  /* Special-case ip-relative addressing */
+  /* Special-case ip-relative addressing.  */
   if (iprel_flag)
     {
       if (mode & I_BIT)
-	{
-	  syntax ();
-	}
+	syntax ();
       else
 	{
-	  memP->opcode |= 5 << 10;	/* IP-relative mode */
+	  memP->opcode |= 5 << 10;	/* IP-relative mode.  */
 	  memP->disp = 32;
 	}
       return;
     }
 
-  /* Handle all other modes */
+  /* Handle all other modes.  */
   switch (mode)
     {
     case D_BIT | A_BIT:
@@ -2151,7 +1046,7 @@ parse_memop (memP, argP, optype)
       break;
 
     case A_BIT | I_BIT:
-      /* set MEMB bit in mode, and OR in mode bits */
+      /* set MEMB bit in mode, and OR in mode bits.  */
       memP->opcode |= mode | MEMB_BIT;
       break;
 
@@ -2161,7 +1056,7 @@ parse_memop (memP, argP, optype)
       /* Fall into next case.  */
     case D_BIT | A_BIT | I_BIT:
     case D_BIT | I_BIT:
-      /* set MEMB bit in mode, and OR in mode bits */
+      /* Set MEMB bit in mode, and OR in mode bits.  */
       memP->opcode |= mode | MEMB_BIT;
       memP->disp = 32;
       break;
@@ -2172,174 +1067,262 @@ parse_memop (memP, argP, optype)
     }
 }
 
-/*****************************************************************************
-   parse_po:	parse machine-dependent pseudo-op
+/* Generate a MEMA- or MEMB-format instruction.  */
 
-  	This is a top-level routine for machine-dependent pseudo-ops.  It slurps
-  	up the rest of the input line, breaks out the individual arguments,
-  	and dispatches them to the correct handler.
-  *************************************************************************** */
 static void
-parse_po (po_num)
-     int po_num;		/* Pseudo-op number:  currently S_LEAFPROC or S_SYSPROC */
+mem_fmt (char *args[],		/* args[0]->opcode mnemonic, args[1-3]->operands.  */
+	 struct i960_opcode *oP,/* Pointer to description of instruction.  */
+	 int callx)		/* Is this a callx opcode.  */
 {
-  /* Pointers operands, with no embedded whitespace.
-     arg[0] unused, arg[1-3]->operands */
-  char *args[4];
-  int n_ops;			/* Number of operands */
-  char *p;			/* Pointer to beginning of unparsed argument string */
-  char eol;			/* Character that indicated end of line */
+  int i;			/* Loop counter.  */
+  struct regop regop;		/* Description of register operand.  */
+  char opdesc;			/* Operand descriptor byte.  */
+  memS instr;			/* Description of binary to be output.  */
+  char *outP;			/* Where the binary was output to.  */
+  expressionS expr;		/* Parsed expression.  */
+  /* ->description of deferred address fixup.  */
+  fixS *fixP;
 
-  extern char is_end_of_line[];
+#ifdef OBJ_COFF
+  /* COFF support isn't in place yet for callx relaxing.  */
+  callx = 0;
+#endif
 
-  /* Advance input pointer to end of line.  */
-  p = input_line_pointer;
-  while (!is_end_of_line[(unsigned char) *input_line_pointer])
-    {
-      input_line_pointer++;
-    }
-  eol = *input_line_pointer;	/* Save end-of-line char */
-  *input_line_pointer = '\0';	/* Terminate argument list */
+  memset (&instr, '\0', sizeof (memS));
+  instr.opcode = oP->opcode;
 
-  /* Parse out operands */
-  n_ops = get_args (p, args);
-  if (n_ops == -1)
+  /* Process operands.  */
+  for (i = 1; i <= oP->num_ops; i++)
     {
-      return;
+      opdesc = oP->operand[i - 1];
+
+      if (MEMOP (opdesc))
+	parse_memop (&instr, args[i], oP->format);
+      else
+	{
+	  parse_regop (&regop, args[i], opdesc);
+	  instr.opcode |= regop.n << 19;
+	}
     }
 
-  /* Dispatch to correct handler */
-  switch (po_num)
+  /* Parse the displacement; this must be done before emitting the
+     opcode, in case it is an expression using `.'.  */
+  parse_expr (instr.e, &expr);
+
+  /* Output opcode.  */
+  outP = emit (instr.opcode);
+
+  if (instr.disp == 0)
+    return;
+
+  /* Process the displacement.  */
+  switch (expr.X_op)
     {
-    case S_SYSPROC:
-      s_sysproc (n_ops, args);
+    case O_illegal:
+      as_bad (_("expression syntax error"));
       break;
-    case S_LEAFPROC:
-      s_leafproc (n_ops, args);
+
+    case O_constant:
+      if (instr.disp == 32)
+	(void) emit (offs (expr));	/* Output displacement.  */
+      else
+	{
+	  /* 12-bit displacement.  */
+	  if (offs (expr) & ~0xfff)
+	    {
+	      /* Won't fit in 12 bits: convert already-output
+	         instruction to MEMB format, output
+	         displacement.  */
+	      mema_to_memb (outP);
+	      (void) emit (offs (expr));
+	    }
+	  else
+	    {
+	      /* WILL fit in 12 bits:  OR into opcode and
+	         overwrite the binary we already put out.  */
+	      instr.opcode |= offs (expr);
+	      md_number_to_chars (outP, instr.opcode, 4);
+	    }
+	}
       break;
+
     default:
-      BAD_CASE (po_num);
+      if (instr.disp == 12)
+	/* Displacement is dependent on a symbol, whose value
+	   may change at link time.  We HAVE to reserve 32 bits.
+	   Convert already-output opcode to MEMB format.  */
+	mema_to_memb (outP);
+
+      /* Output 0 displacement and set up address fixup for when
+         this symbol's value becomes known.  */
+      outP = emit ((long) 0);
+      fixP = fix_new_exp (frag_now,
+			  outP - frag_now->fr_literal,
+			  4, & expr, 0, NO_RELOC);
+      /* Steve's linker relaxing hack.  Mark this 32-bit relocation as
+         being in the instruction stream, specifically as part of a callx
+         instruction.  */
+      fixP->fx_bsr = callx;
       break;
     }
-
-  /* Restore eol, so line numbers get updated correctly.  Base
-     assembler assumes we leave input pointer pointing at char
-     following the eol.  */
-  *input_line_pointer++ = eol;
 }
 
-/*****************************************************************************
-   parse_regop: parse a register operand.
+/* targ_has_iclass:
 
-  	In case of illegal operand, issue a message and return some valid
-  	information so instruction processing can continue.
-  *************************************************************************** */
-static void
-parse_regop (regopP, optext, opdesc)
-     struct regop *regopP;	/* Where to put description of register operand */
-     char *optext;		/* Text of operand */
-     char opdesc;		/* Descriptor byte:  what's legal for this operand */
+   Return TRUE iff the target architecture supports the indicated
+   class of instructions.  */
+
+static int
+targ_has_iclass (int ic) /* Instruction class;  one of:
+			    I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM, I_CX2, I_HX, I_HX2.  */
 {
-  int n;			/* Register number */
-  expressionS e;		/* Parsed expression */
+  iclasses_seen |= ic;
 
-  /* See if operand is a register */
-  n = get_regnum (optext);
-  if (n >= 0)
+  switch (architecture)
     {
-      if (IS_RG_REG (n))
+    case ARCH_KA:
+      return ic & (I_BASE | I_KX);
+    case ARCH_KB:
+      return ic & (I_BASE | I_KX | I_FP | I_DEC);
+    case ARCH_MC:
+      return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL);
+    case ARCH_CA:
+      return ic & (I_BASE | I_CX | I_CX2 | I_CASIM);
+    case ARCH_JX:
+      return ic & (I_BASE | I_CX2 | I_JX);
+    case ARCH_HX:
+      return ic & (I_BASE | I_CX2 | I_JX | I_HX);
+    default:
+      if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL))
+	  && (iclasses_seen & (I_CX | I_CX2)))
 	{
-	  /* global or local register */
-	  if (!REG_ALIGN (opdesc, n))
-	    {
-	      as_bad (_("unaligned register"));
-	    }
-	  regopP->n = n;
-	  regopP->mode = 0;
-	  regopP->special = 0;
-	  return;
+	  as_warn (_("architecture of opcode conflicts with that of earlier instruction(s)"));
+	  iclasses_seen &= ~ic;
 	}
-      else if (IS_FP_REG (n) && FP_OK (opdesc))
+      return 1;
+    }
+}
+
+/* shift_ok:
+   Determine if a "shlo" instruction can be used to implement a "ldconst".
+   This means that some number X < 32 can be shifted left to produce the
+   constant of interest.
+
+   Return the shift count, or 0 if we can't do it.
+   Caller calculates X by shifting original constant right 'shift' places.  */
+
+static int
+shift_ok (int n)		/* The constant of interest.  */
+{
+  int shift;			/* The shift count.  */
+
+  if (n <= 0)
+    /* Can't do it for negative numbers.  */
+    return 0;
+
+  /* Shift 'n' right until a 1 is about to be lost.  */
+  for (shift = 0; (n & 1) == 0; shift++)
+    n >>= 1;
+
+  if (n >= 32)
+    return 0;
+
+  return shift;
+}
+
+/* parse_ldcont:
+   Parse and replace a 'ldconst' pseudo-instruction with an appropriate
+   i80960 instruction.
+
+   Assumes the input consists of:
+  		arg[0]	opcode mnemonic ('ldconst')
+  		arg[1]  first operand (constant)
+  		arg[2]	name of register to be loaded
+
+   Replaces opcode and/or operands as appropriate.
+
+   Returns the new number of arguments, or -1 on failure.  */
+
+static int
+parse_ldconst (char *arg[])	/* See above.  */
+{
+  int n;			/* Constant to be loaded.  */
+  int shift;			/* Shift count for "shlo" instruction.  */
+  static char buf[5];		/* Literal for first operand.  */
+  static char buf2[5];		/* Literal for second operand.  */
+  expressionS e;		/* Parsed expression.  */
+
+  arg[3] = NULL;		/* So we can tell at the end if it got used or not.  */
+
+  parse_expr (arg[1], &e);
+  switch (e.X_op)
+    {
+    default:
+      /* We're dependent on one or more symbols -- use "lda".  */
+      arg[0] = "lda";
+      break;
+
+    case O_constant:
+      /* Try the following mappings:
+              ldconst   0,<reg>  -> mov  0,<reg>
+              ldconst  31,<reg>  -> mov  31,<reg>
+              ldconst  32,<reg>  -> addo 1,31,<reg>
+              ldconst  62,<reg>  -> addo 31,31,<reg>
+              ldconst  64,<reg>  -> shlo 8,3,<reg>
+              ldconst  -1,<reg>  -> subo 1,0,<reg>
+              ldconst -31,<reg>  -> subo 31,0,<reg>
+        
+         Anything else becomes:
+                lda xxx,<reg>.  */
+      n = offs (e);
+      if ((0 <= n) && (n <= 31))
+	arg[0] = "mov";
+      else if ((-31 <= n) && (n <= -1))
 	{
-	  /* Floating point register, and it's allowed */
-	  regopP->n = n - FP0;
-	  regopP->mode = 1;
-	  regopP->special = 0;
-	  return;
+	  arg[0] = "subo";
+	  arg[3] = arg[2];
+	  sprintf (buf, "%d", -n);
+	  arg[1] = buf;
+	  arg[2] = "0";
 	}
-      else if (IS_SF_REG (n) && SFR_OK (opdesc))
+      else if ((32 <= n) && (n <= 62))
 	{
-	  /* Special-function register, and it's allowed */
-	  regopP->n = n - SF0;
-	  regopP->mode = 0;
-	  regopP->special = 1;
-	  if (!targ_has_sfr (regopP->n))
-	    {
-	      as_bad (_("no such sfr in this architecture"));
-	    }
-	  return;
+	  arg[0] = "addo";
+	  arg[3] = arg[2];
+	  arg[1] = "31";
+	  sprintf (buf, "%d", n - 31);
+	  arg[2] = buf;
 	}
-    }
-  else if (LIT_OK (opdesc))
-    {
-      /* How about a literal?  */
-      regopP->mode = 1;
-      regopP->special = 0;
-      if (FP_OK (opdesc))
-	{			/* floating point literal acceptable */
-	  /* Skip over 0f, 0d, or 0e prefix */
-	  if ((optext[0] == '0')
-	      && (optext[1] >= 'd')
-	      && (optext[1] <= 'f'))
-	    {
-	      optext += 2;
-	    }
-
-	  if (!strcmp (optext, "0.0") || !strcmp (optext, "0"))
-	    {
-	      regopP->n = 0x10;
-	      return;
-	    }
-	  if (!strcmp (optext, "1.0") || !strcmp (optext, "1"))
-	    {
-	      regopP->n = 0x16;
-	      return;
-	    }
-
+      else if ((shift = shift_ok (n)) != 0)
+	{
+	  arg[0] = "shlo";
+	  arg[3] = arg[2];
+	  sprintf (buf, "%d", shift);
+	  arg[1] = buf;
+	  sprintf (buf2, "%d", n >> shift);
+	  arg[2] = buf2;
 	}
       else
-	{			/* fixed point literal acceptable */
-	  parse_expr (optext, &e);
-	  if (e.X_op != O_constant
-	      || (offs (e) < 0) || (offs (e) > 31))
-	    {
-	      as_bad (_("illegal literal"));
-	      offs (e) = 0;
-	    }
-	  regopP->n = offs (e);
-	  return;
-	}
-    }
+	arg[0] = "lda";
+      break;
 
-  /* Nothing worked */
-  syntax ();
-  regopP->mode = 0;		/* Register r0 is always a good one */
-  regopP->n = 0;
-  regopP->special = 0;
-}				/* parse_regop() */
+    case O_illegal:
+      as_bad (_("invalid constant"));
+      return -1;
+      break;
+    }
+  return (arg[3] == 0) ? 2 : 3;
+}
 
-/*****************************************************************************
-   reg_fmt:	generate a REG-format instruction
+/* reg_fmt:	generate a REG-format instruction.  */
 
-  *************************************************************************** */
 static void
-reg_fmt (args, oP)
-     char *args[];		/* args[0]->opcode mnemonic, args[1-3]->operands */
-     struct i960_opcode *oP;	/* Pointer to description of instruction */
+reg_fmt (char *args[],		/* args[0]->opcode mnemonic, args[1-3]->operands.  */
+	 struct i960_opcode *oP)/* Pointer to description of instruction.  */
 {
-  long instr;			/* Binary to be output */
-  struct regop regop;		/* Description of register operand */
-  int n_ops;			/* Number of operands */
+  long instr;			/* Binary to be output.  */
+  struct regop regop;		/* Description of register operand.  */
+  int n_ops;			/* Number of operands.  */
 
   instr = oP->opcode;
   n_ops = oP->num_ops;
@@ -2351,19 +1334,16 @@ reg_fmt (args, oP)
       if ((n_ops == 1) && !(instr & M3))
 	{
 	  /* 1-operand instruction in which the dst field should
-	     * be used (instead of src1).
-	   */
+	     be used (instead of src1).  */
 	  regop.n <<= 19;
 	  if (regop.special)
-	    {
-	      regop.mode = regop.special;
-	    }
+	    regop.mode = regop.special;
 	  regop.mode <<= 13;
 	  regop.special = 0;
 	}
       else
 	{
-	  /* regop.n goes in bit 0, needs no shifting */
+	  /* regop.n goes in bit 0, needs no shifting.  */
 	  regop.mode <<= 11;
 	  regop.special <<= 5;
 	}
@@ -2377,13 +1357,10 @@ reg_fmt (args, oP)
       if ((n_ops == 2) && !(instr & M3))
 	{
 	  /* 2-operand instruction in which the dst field should
-	     * be used instead of src2).
-	   */
+	     be used instead of src2).  */
 	  regop.n <<= 19;
 	  if (regop.special)
-	    {
-	      regop.mode = regop.special;
-	    }
+	    regop.mode = regop.special;
 	  regop.mode <<= 13;
 	  regop.special = 0;
 	}
@@ -2399,24 +1376,595 @@ reg_fmt (args, oP)
     {
       parse_regop (&regop, args[3], oP->operand[2]);
       if (regop.special)
-	{
-	  regop.mode = regop.special;
-	}
+	regop.mode = regop.special;
       instr |= (regop.n <<= 19) | (regop.mode <<= 13);
     }
   emit (instr);
 }
 
-/*****************************************************************************
-   relax_cobr:
-  	Replace cobr instruction in a code fragment with equivalent branch and
-  	compare instructions, so it can reach beyond a 13-bit displacement.
-  	Set up an address fix/relocation for the new branch instruction.
+/* get_args:	break individual arguments out of comma-separated list
+
+   Input assumptions:
+  	- all comments and labels have been removed
+  	- all strings of whitespace have been collapsed to a single blank.
+  	- all character constants ('x') have been replaced with decimal
 
-  *************************************************************************** */
+   Output:
+  	args[0] is untouched. args[1] points to first operand, etc. All args:
+  	- are NULL-terminated
+  	- contain no whitespace
+
+   Return value:
+   Number of operands (0,1,2, or 3) or -1 on error.  */
+
+static int
+get_args (char *p, 	/* Pointer to comma-separated operands; Mucked by us.  */
+	  char *args[]) /* Output arg: pointers to operands placed in args[1-3].
+			   Must accommodate 4 entries (args[0-3]).  */
+
+{
+  int n;		/* Number of operands.  */
+  char *to;
+
+  /* Skip lead white space.  */
+  while (*p == ' ')
+    p++;
+
+  if (*p == '\0')
+    return 0;
+
+  n = 1;
+  args[1] = p;
+
+  /* Squeze blanks out by moving non-blanks toward start of string.
+     Isolate operands, whenever comma is found.  */
+  to = p;
+  while (*p != '\0')
+    {
+      if (*p == ' '
+	  && (! ISALNUM (p[1])
+	      || ! ISALNUM (p[-1])))
+	p++;
+      else if (*p == ',')
+	{
+	  /* Start of operand.  */
+	  if (n == 3)
+	    {
+	      as_bad (_("too many operands"));
+	      return -1;
+	    }
+	  *to++ = '\0';		/* Terminate argument.  */
+	  args[++n] = to;	/* Start next argument.  */
+	  p++;
+	}
+      else
+	*to++ = *p++;
+    }
+  *to = '\0';
+  return n;
+}
+
+/* i_scan:	perform lexical scan of ascii assembler instruction.
+
+   Input assumptions:
+  	- input string is an i80960 instruction (not a pseudo-op)
+  	- all comments and labels have been removed
+  	- all strings of whitespace have been collapsed to a single blank.
+
+   Output:
+  	args[0] points to opcode, other entries point to operands. All strings:
+  	- are NULL-terminated
+  	- contain no whitespace
+  	- have character constants ('x') replaced with a decimal number
+
+   Return value:
+     Number of operands (0,1,2, or 3) or -1 on error.  */
+
+static int
+i_scan (char *iP,     /* Pointer to ascii instruction;  Mucked by us.  */
+	char *args[]) /* Output arg: pointers to opcode and operands placed here.
+			 Must accommodate 4 entries.  */
+{
+  /* Isolate opcode.  */
+  if (*(iP) == ' ')
+    iP++;
+
+  args[0] = iP;
+  for (; *iP != ' '; iP++)
+    {
+      if (*iP == '\0')
+	{
+	  /* There are no operands.  */
+	  if (args[0] == iP)
+	    {
+	      /* We never moved: there was no opcode either!  */
+	      as_bad (_("missing opcode"));
+	      return -1;
+	    }
+	  return 0;
+	}
+    }
+  *iP++ = '\0';
+  return (get_args (iP, args));
+}
+
+static void
+brcnt_emit (void)
+{
+  /* Emit call to "increment" routine.  */
+  ctrl_fmt (BR_CNT_FUNC, CALL, 1);
+  /* Emit inline counter to be incremented.  */
+  emit (0);
+}
+
+static char *
+brlab_next (void)
+{
+  static char buf[20];
+
+  sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++);
+  return buf;
+}
+
+static void
+ctrl_fmt (char *targP,		/* Pointer to text of lone operand (if any).  */
+	  long opcode,		/* Template of instruction.  */
+	  int num_ops)		/* Number of operands.  */
+{
+  int instrument;		/* TRUE iff we should add instrumentation to track
+				   how often the branch is taken.  */
+
+  if (num_ops == 0)
+    emit (opcode);		/* Output opcode.  */
+  else
+    {
+      instrument = instrument_branches && (opcode != CALL)
+	&& (opcode != B) && (opcode != RET) && (opcode != BAL);
+
+      if (instrument)
+	{
+	  brcnt_emit ();
+	  colon (brlab_next ());
+	}
+
+      /* The operand MUST be an ip-relative displacement. Parse it
+         and set up address fix for the instruction we just output.  */
+      get_cdisp (targP, "CTRL", opcode, 24, 0, 0);
+
+      if (instrument)
+	brcnt_emit ();
+    }
+}
+
+static void
+cobr_fmt (/* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */
+	  char *arg[],
+	  /* Opcode, with branch-prediction bits already set if necessary.  */
+	  long opcode,
+	  /* Pointer to description of instruction.  */
+	  struct i960_opcode *oP)
+{
+  long instr;			/* 32-bit instruction.  */
+  struct regop regop;		/* Description of register operand.  */
+  int n;			/* Number of operands.  */
+  int var_frag;			/* 1 if varying length code fragment should
+				     be emitted;  0 if an address fix
+				        should be emitted.  */
+
+  instr = opcode;
+  n = oP->num_ops;
+
+  if (n >= 1)
+    {
+      /* First operand (if any) of a COBR is always a register
+	 operand.  Parse it.  */
+      parse_regop (&regop, arg[1], oP->operand[0]);
+      instr |= (regop.n << 19) | (regop.mode << 13);
+    }
+
+  if (n >= 2)
+    {
+      /* Second operand (if any) of a COBR is always a register
+	 operand.  Parse it.  */
+      parse_regop (&regop, arg[2], oP->operand[1]);
+      instr |= (regop.n << 14) | regop.special;
+    }
+
+  if (n < 3)
+    emit (instr);
+  else
+    {
+      if (instrument_branches)
+	{
+	  brcnt_emit ();
+	  colon (brlab_next ());
+	}
+
+      /* A third operand to a COBR is always a displacement.  Parse
+         it; if it's relaxable (a cobr "j" directive, or any cobr
+         other than bbs/bbc when the "-norelax" option is not in use)
+         set up a variable code fragment; otherwise set up an address
+         fix.  */
+      var_frag = !norelax || (oP->format == COJ);	/* TRUE or FALSE */
+      get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0);
+
+      if (instrument_branches)
+	brcnt_emit ();
+    }
+}
+
+/* Assumptions about the passed-in text:
+  	- all comments, labels removed
+  	- text is an instruction
+  	- all white space compressed to single blanks
+  	- all character constants have been replaced with decimal.  */
+
+void
+md_assemble (char *textP)
+{
+  /* Parsed instruction text, containing NO whitespace: arg[0]->opcode
+     mnemonic arg[1-3]->operands, with char constants replaced by
+     decimal numbers.  */
+  char *args[4];
+  /* Number of instruction operands.  */
+  int n_ops;
+  /* Pointer to instruction description.  */
+  struct i960_opcode *oP;
+  /* TRUE iff opcode mnemonic included branch-prediction suffix (".f"
+     or ".t").  */
+  int branch_predict;
+  /* Setting of branch-prediction bit(s) to be OR'd into instruction
+     opcode of CTRL/COBR format instructions.  */
+  long bp_bits;
+  /* Offset of last character in opcode mnemonic.  */
+  int n;
+  const char *bp_error_msg = _("branch prediction invalid on this opcode");
+
+  /* Parse instruction into opcode and operands.  */
+  memset (args, '\0', sizeof (args));
+
+  n_ops = i_scan (textP, args);
+
+  if (n_ops == -1)
+    return;			/* Error message already issued.  */
+
+  /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction.  */
+  if (!strcmp (args[0], "ldconst"))
+    {
+      n_ops = parse_ldconst (args);
+      if (n_ops == -1)
+	return;
+    }
+
+  /* Check for branch-prediction suffix on opcode mnemonic, strip it off.  */
+  n = strlen (args[0]) - 1;
+  branch_predict = 0;
+  bp_bits = 0;
+
+  if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f'))
+    {
+      /* We could check here to see if the target architecture
+	 supports branch prediction, but why bother?  The bit will
+	 just be ignored by processors that don't use it.  */
+      branch_predict = 1;
+      bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN;
+      args[0][n - 1] = '\0';	/* Strip suffix from opcode mnemonic */
+    }
+
+  /* Look up opcode mnemonic in table and check number of operands.
+     Check that opcode is legal for the target architecture.  If all
+     looks good, assemble instruction.  */
+  oP = (struct i960_opcode *) hash_find (op_hash, args[0]);
+  if (!oP || !targ_has_iclass (oP->iclass))
+    as_bad (_("invalid opcode, \"%s\"."), args[0]);
+  else if (n_ops != oP->num_ops)
+    as_bad (_("improper number of operands.  expecting %d, got %d"),
+	    oP->num_ops, n_ops);
+  else
+    {
+      switch (oP->format)
+	{
+	case FBRA:
+	case CTRL:
+	  ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops);
+	  if (oP->format == FBRA)
+	    /* Now generate a 'bno' to same arg */
+	    ctrl_fmt (args[1], BNO | bp_bits, 1);
+	  break;
+	case COBR:
+	case COJ:
+	  cobr_fmt (args, oP->opcode | bp_bits, oP);
+	  break;
+	case REG:
+	  if (branch_predict)
+	    as_warn (bp_error_msg);
+	  reg_fmt (args, oP);
+	  break;
+	case MEM1:
+	  if (args[0][0] == 'c' && args[0][1] == 'a')
+	    {
+	      if (branch_predict)
+		as_warn (bp_error_msg);
+	      mem_fmt (args, oP, 1);
+	      break;
+	    }
+	case MEM2:
+	case MEM4:
+	case MEM8:
+	case MEM12:
+	case MEM16:
+	  if (branch_predict)
+	    as_warn (bp_error_msg);
+	  mem_fmt (args, oP, 0);
+	  break;
+	case CALLJ:
+	  if (branch_predict)
+	    as_warn (bp_error_msg);
+	  /* Output opcode & set up "fixup" (relocation); flag
+	     relocation as 'callj' type.  */
+	  know (oP->num_ops == 1);
+	  get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1);
+	  break;
+	default:
+	  BAD_CASE (oP->format);
+	  break;
+	}
+    }
+}
+
+void
+md_number_to_chars (char *buf,
+		    valueT value,
+		    int n)
+{
+  number_to_chars_littleendian (buf, value, n);
+}
+
+#define MAX_LITTLENUMS	6
+#define LNUM_SIZE	sizeof (LITTLENUM_TYPE)
+
+/* md_atof:	convert ascii to floating point
+
+   Turn a string at input_line_pointer into a floating point constant of type
+   'type', and store the appropriate bytes at *litP.  The number of LITTLENUMS
+   emitted is returned at 'sizeP'.  An error message is returned, or a pointer
+   to an empty message if OK.
+
+   Note we call the i386 floating point routine, rather than complicating
+   things with more files or symbolic links.  */
+
+char *
+md_atof (int type, char *litP, int *sizeP)
+{
+  LITTLENUM_TYPE words[MAX_LITTLENUMS];
+  LITTLENUM_TYPE *wordP;
+  int prec;
+  char *t;
+
+  switch (type)
+    {
+    case 'f':
+    case 'F':
+      prec = 2;
+      break;
+
+    case 'd':
+    case 'D':
+      prec = 4;
+      break;
+
+    case 't':
+    case 'T':
+      prec = 5;
+      type = 'x';		/* That's what atof_ieee() understands.  */
+      break;
+
+    default:
+      *sizeP = 0;
+      return _("Bad call to md_atof()");
+    }
+
+  t = atof_ieee (input_line_pointer, type, words);
+  if (t)
+    input_line_pointer = t;
+
+  *sizeP = prec * LNUM_SIZE;
+
+  /* Output the LITTLENUMs in REVERSE order in accord with i80960
+     word-order.  (Dunno why atof_ieee doesn't do it in the right
+     order in the first place -- probably because it's a hack of
+     atof_m68k.)  */
+  for (wordP = words + prec - 1; prec--;)
+    {
+      md_number_to_chars (litP, (long) (*wordP--), LNUM_SIZE);
+      litP += sizeof (LITTLENUM_TYPE);
+    }
+
+  return 0;
+}
+
+static void
+md_number_to_imm (char *buf, long val, int n)
+{
+  md_number_to_chars (buf, val, n);
+}
+
+static void
+md_number_to_field (char *instrP,		/* Pointer to instruction to be fixed.  */
+		    long val,			/* Address fixup value.  */
+		    bit_fixS *bfixP)		/* Description of bit field to be fixed up.  */
+{
+  int numbits;			/* Length of bit field to be fixed.  */
+  long instr;			/* 32-bit instruction to be fixed-up.  */
+  long sign;			/* 0 or -1, according to sign bit of 'val'.  */
+
+  /* Convert instruction back to host byte order.  */
+  instr = md_chars_to_number (instrP, 4);
+
+  /* Surprise! -- we stored the number of bits to be modified rather
+     than a pointer to a structure.  */
+  numbits = (int) (size_t) bfixP;
+  if (numbits == 1)
+    /* This is a no-op, stuck here by reloc_callj().  */
+    return;
+
+  know ((numbits == 13) || (numbits == 24));
+
+  /* Propagate sign bit of 'val' for the given number of bits.  Result
+     should be all 0 or all 1.  */
+  sign = val >> ((int) numbits - 1);
+  if (((val < 0) && (sign != -1))
+      || ((val > 0) && (sign != 0)))
+    as_bad (_("Fixup of %ld too large for field width of %d"),
+	    val, numbits);
+  else
+    {
+      /* Put bit field into instruction and write back in target
+         * byte order.  */
+      val &= ~(-1 << (int) numbits);	/* Clear unused sign bits.  */
+      instr |= val;
+      md_number_to_chars (instrP, instr, 4);
+    }
+}
+
+
+/* md_parse_option
+  	Invocation line includes a switch not recognized by the base assembler.
+  	See if it's a processor-specific option.  For the 960, these are:
+
+  	-norelax:
+  		Conditional branch instructions that require displacements
+  		greater than 13 bits (or that have external targets) should
+  		generate errors.  The default is to replace each such
+  		instruction with the corresponding compare (or chkbit) and
+  		branch instructions.  Note that the Intel "j" cobr directives
+  		are ALWAYS "de-optimized" in this way when necessary,
+  		regardless of the setting of this option.
+
+  	-b:
+  		Add code to collect information about branches taken, for
+  		later optimization of branch prediction bits by a separate
+  		tool.  COBR and CNTL format instructions have branch
+  		prediction bits (in the CX architecture);  if "BR" represents
+  		an instruction in one of these classes, the following rep-
+  		resents the code generated by the assembler:
+
+  			call	<increment routine>
+  			.word	0	# pre-counter
+  		Label:  BR
+  			call	<increment routine>
+  			.word	0	# post-counter
+
+  		A table of all such "Labels" is also generated.
+
+  	-AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
+  		Select the 80960 architecture.  Instructions or features not
+  		supported by the selected architecture cause fatal errors.
+  		The default is to generate code for any instruction or feature
+  		that is supported by SOME version of the 960 (even if this
+  		means mixing architectures!).  */
+
+const char *md_shortopts = "A:b";
+struct option md_longopts[] =
+{
+#define OPTION_LINKRELAX (OPTION_MD_BASE)
+  {"linkrelax", no_argument, NULL, OPTION_LINKRELAX},
+  {"link-relax", no_argument, NULL, OPTION_LINKRELAX},
+#define OPTION_NORELAX (OPTION_MD_BASE + 1)
+  {"norelax", no_argument, NULL, OPTION_NORELAX},
+  {"no-relax", no_argument, NULL, OPTION_NORELAX},
+  {NULL, no_argument, NULL, 0}
+};
+size_t md_longopts_size = sizeof (md_longopts);
+
+struct tabentry
+{
+  char *flag;
+  int arch;
+};
+static const struct tabentry arch_tab[] =
+{
+  {"KA", ARCH_KA},
+  {"KB", ARCH_KB},
+  {"SA", ARCH_KA},		/* Synonym for KA.  */
+  {"SB", ARCH_KB},		/* Synonym for KB.  */
+  {"KC", ARCH_MC},		/* Synonym for MC.  */
+  {"MC", ARCH_MC},
+  {"CA", ARCH_CA},
+  {"JX", ARCH_JX},
+  {"HX", ARCH_HX},
+  {NULL, 0}
+};
+
+int
+md_parse_option (int c, char *arg)
+{
+  switch (c)
+    {
+    case OPTION_LINKRELAX:
+      linkrelax = 1;
+      flag_keep_locals = 1;
+      break;
+
+    case OPTION_NORELAX:
+      norelax = 1;
+      break;
+
+    case 'b':
+      instrument_branches = 1;
+      break;
+
+    case 'A':
+      {
+	const struct tabentry *tp;
+	char *p = arg;
+
+	for (tp = arch_tab; tp->flag != NULL; tp++)
+	  if (!strcmp (p, tp->flag))
+	    break;
+
+	if (tp->flag == NULL)
+	  {
+	    as_bad (_("invalid architecture %s"), p);
+	    return 0;
+	  }
+	else
+	  architecture = tp->arch;
+      }
+      break;
+
+    default:
+      return 0;
+    }
+
+  return 1;
+}
+
+void
+md_show_usage (FILE *stream)
+{
+  int i;
+
+  fprintf (stream, _("I960 options:\n"));
+  for (i = 0; arch_tab[i].flag; i++)
+    fprintf (stream, "%s-A%s", i ? " | " : "", arch_tab[i].flag);
+  fprintf (stream, _("\n\
+			specify variant of 960 architecture\n\
+-b			add code to collect statistics about branches taken\n\
+-link-relax		preserve individual alignment directives so linker\n\
+			can do relaxing (b.out format only)\n\
+-no-relax		don't alter compare-and-branch instructions for\n\
+			long displacements\n"));
+}
+
+/* relax_cobr:
+   Replace cobr instruction in a code fragment with equivalent branch and
+   compare instructions, so it can reach beyond a 13-bit displacement.
+   Set up an address fix/relocation for the new branch instruction.  */
 
 /* This "conditional jump" table maps cobr instructions into
    equivalent compare and branch opcodes.  */
+
 static const
 struct
 {
@@ -2445,39 +1993,37 @@ coj[] =
 };
 
 static void
-relax_cobr (fragP)
-     register fragS *fragP;	/* fragP->fr_opcode is assumed to point to
-				 * the cobr instruction, which comes at the
-				 * end of the code fragment.
-				 */
+relax_cobr (fragS *fragP)	/* fragP->fr_opcode is assumed to point to
+				   the cobr instruction, which comes at the
+				   end of the code fragment.  */
 {
   int opcode, src1, src2, m1, s2;
-  /* Bit fields from cobr instruction */
-  long bp_bits;			/* Branch prediction bits from cobr instruction */
-  long instr;			/* A single i960 instruction */
-  /* ->instruction to be replaced */
+  /* Bit fields from cobr instruction.  */
+  long bp_bits;			/* Branch prediction bits from cobr instruction.  */
+  long instr;			/* A single i960 instruction.  */
+  /* ->instruction to be replaced.  */
   char *iP;
-  fixS *fixP;			/* Relocation that can be done at assembly time */
+  fixS *fixP;			/* Relocation that can be done at assembly time.  */
 
-  /* PICK UP & PARSE COBR INSTRUCTION */
+  /* Pick up & parse cobr instruction.  */
   iP = fragP->fr_opcode;
   instr = md_chars_to_number (iP, 4);
-  opcode = ((instr >> 24) & 0xff) - 0x30;	/* "-0x30" for table index */
+  opcode = ((instr >> 24) & 0xff) - 0x30;	/* "-0x30" for table index.  */
   src1 = (instr >> 19) & 0x1f;
   m1 = (instr >> 13) & 1;
   s2 = instr & 1;
   src2 = (instr >> 14) & 0x1f;
   bp_bits = instr & BP_MASK;
 
-  /* GENERATE AND OUTPUT COMPARE INSTRUCTION */
+  /* Generate and output compare instruction.  */
   instr = coj[opcode].compare
     | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14);
   md_number_to_chars (iP, instr, 4);
 
-  /* OUTPUT BRANCH INSTRUCTION */
+  /* Output branch instruction.  */
   md_number_to_chars (iP + 4, coj[opcode].branch | bp_bits, 4);
 
-  /* SET UP ADDRESS FIXUP/RELOCATION */
+  /* Set up address fixup/relocation.  */
   fixP = fix_new (fragP,
 		  iP + 4 - fragP->fr_literal,
 		  4,
@@ -2486,81 +2032,172 @@ relax_cobr (fragP)
 		  1,
 		  NO_RELOC);
 
-  fixP->fx_bit_fixP = (bit_fixS *) 24;	/* Store size of bit field */
+  fixP->fx_bit_fixP = (bit_fixS *) 24;	/* Store size of bit field.  */
 
   fragP->fr_fix += 4;
   frag_wane (fragP);
 }
 
-/*****************************************************************************
-   reloc_callj:	Relocate a 'callj' instruction
+/* md_convert_frag:
 
-  	This is a "non-(GNU)-standard" machine-dependent hook.  The base
-  	assembler calls it when it decides it can relocate an address at
-  	assembly time instead of emitting a relocation directive.
+   Called by base assembler after address relaxation is finished:  modify
+   variable fragments according to how much relaxation was done.
 
-  	Check to see if the relocation involves a 'callj' instruction to a:
-  	    sysproc:	Replace the default 'call' instruction with a 'calls'
-  	    leafproc:	Replace the default 'call' instruction with a 'bal'.
-  	    other proc:	Do nothing.
-
-  	See b.out.h for details on the 'n_other' field in a symbol structure.
+   If the fragment substate is still 1, a 13-bit displacement was enough
+   to reach the symbol in question.  Set up an address fixup, but otherwise
+   leave the cobr instruction alone.
 
-   IMPORTANT!:
-  	Assumes the caller has already figured out, in the case of a leafproc,
-  	to use the 'bal' entry point, and has substituted that symbol into the
-  	passed fixup structure.
+   If the fragment substate is 2, a 13-bit displacement was not enough.
+   Replace the cobr with a two instructions (a compare and a branch).  */
 
-  *************************************************************************** */
-int
-reloc_callj (fixP)
-     /* Relocation that can be done at assembly time */
-     fixS *fixP;
+#ifndef BFD_ASSEMBLER
+void
+md_convert_frag (object_headers *headers ATTRIBUTE_UNUSED,
+		 segT seg ATTRIBUTE_UNUSED,
+		 fragS *fragP)
+#else
+void
+md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED,
+		 segT sec ATTRIBUTE_UNUSED,
+		 fragS *fragP)
+#endif
 {
-  /* Points to the binary for the instruction being relocated.  */
-  char *where;
+  /* Structure describing needed address fix.  */
+  fixS *fixP;
 
-  if (!fixP->fx_tcbit)
+  switch (fragP->fr_subtype)
     {
-      /* This wasn't a callj instruction in the first place */
-      return 0;
+    case 1:
+      /* Leave single cobr instruction.  */
+      fixP = fix_new (fragP,
+		      fragP->fr_opcode - fragP->fr_literal,
+		      4,
+		      fragP->fr_symbol,
+		      fragP->fr_offset,
+		      1,
+		      NO_RELOC);
+
+      fixP->fx_bit_fixP = (bit_fixS *) 13;	/* Size of bit field.  */
+      break;
+    case 2:
+      /* Replace cobr with compare/branch instructions.  */
+      relax_cobr (fragP);
+      break;
+    default:
+      BAD_CASE (fragP->fr_subtype);
+      break;
     }
+}
 
-  where = fixP->fx_frag->fr_literal + fixP->fx_where;
+/* md_estimate_size_before_relax:  How much does it look like *fragP will grow?
 
-  if (TC_S_IS_SYSPROC (fixP->fx_addsy))
-    {
-      /* Symbol is a .sysproc: replace 'call' with 'calls'.  System
-         procedure number is (other-1).  */
-      md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4);
+   Called by base assembler just before address relaxation.
+   Return the amount by which the fragment will grow.
 
-      /* Nothing else needs to be done for this instruction.  Make
-         sure 'md_number_to_field()' will perform a no-op.  */
-      fixP->fx_bit_fixP = (bit_fixS *) 1;
-    }
-  else if (TC_S_IS_CALLNAME (fixP->fx_addsy))
+   Any symbol that is now undefined will not become defined; cobr's
+   based on undefined symbols will have to be replaced with a compare
+   instruction and a branch instruction, and the code fragment will grow
+   by 4 bytes.  */
+
+int
+md_estimate_size_before_relax (fragS *fragP, segT segment_type)
+{
+  /* If symbol is undefined in this segment, go to "relaxed" state
+     (compare and branch instructions instead of cobr) right now.  */
+  if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type)
     {
-      /* Should not happen: see block comment above */
-      as_fatal (_("Trying to 'bal' to %s"), S_GET_NAME (fixP->fx_addsy));
+      relax_cobr (fragP);
+      return 4;
     }
-  else if (TC_S_IS_BALNAME (fixP->fx_addsy))
+
+  return md_relax_table[fragP->fr_subtype].rlx_length;
+}
+
+#if defined(OBJ_AOUT) | defined(OBJ_BOUT)
+
+/* md_ri_to_chars:
+   This routine exists in order to overcome machine byte-order problems
+   when dealing with bit-field entries in the relocation_info struct.
+
+   But relocation info will be used on the host machine only (only
+   executable code is actually downloaded to the i80960).  Therefore,
+   we leave it in host byte order.  */
+
+static void
+md_ri_to_chars (char *where, struct relocation_info *ri)
+{
+  host_number_to_chars (where, ri->r_address, 4);
+  host_number_to_chars (where + 4, ri->r_index, 3);
+#if WORDS_BIGENDIAN
+  where[7] = (ri->r_pcrel << 7
+	      | ri->r_length << 5
+	      | ri->r_extern << 4
+	      | ri->r_bsr << 3
+	      | ri->r_disp << 2
+	      | ri->r_callj << 1
+	      | ri->nuthin << 0);
+#else
+  where[7] = (ri->r_pcrel << 0
+	      | ri->r_length << 1
+	      | ri->r_extern << 3
+	      | ri->r_bsr << 4
+	      | ri->r_disp << 5
+	      | ri->r_callj << 6
+	      | ri->nuthin << 7);
+#endif
+}
+
+#endif /* defined(OBJ_AOUT) | defined(OBJ_BOUT) */
+
+
+/* brtab_emit:	generate the fetch-prediction branch table.
+
+   See the comments above the declaration of 'br_cnt' for details on
+   branch-prediction instrumentation.
+
+   The code emitted here would be functionally equivalent to the following
+   example assembler source.
+
+  			.data
+  			.align	2
+  	   BR_TAB_NAME:
+  			.word	0		# link to next table
+  			.word	3		# length of table
+  			.word	LBRANCH0	# 1st entry in table proper
+  			.word	LBRANCH1
+  			.word	LBRANCH2  */
+
+void
+brtab_emit (void)
+{
+  int i;
+  char buf[20];
+  /* Where the binary was output to.  */
+  char *p;
+  /* Pointer to description of deferred address fixup.  */
+  fixS *fixP;
+
+  if (!instrument_branches)
+    return;
+
+  subseg_set (data_section, 0);	/*      .data */
+  frag_align (2, 0, 0);		/*      .align 2 */
+  record_alignment (now_seg, 2);
+  colon (BR_TAB_NAME);		/* BR_TAB_NAME: */
+  emit (0);			/*      .word 0 #link to next table */
+  emit (br_cnt);		/*      .word n #length of table */
+
+  for (i = 0; i < br_cnt; i++)
     {
-      /* Replace 'call' with 'bal'; both instructions have the same
-         format, so calling code should complete relocation as if
-         nothing happened here.  */
-      md_number_to_chars (where, BAL, 4);
+      sprintf (buf, "%s%d", BR_LABEL_BASE, i);
+      p = emit (0);
+      fixP = fix_new (frag_now,
+		      p - frag_now->fr_literal,
+		      4, symbol_find (buf), 0, 0, NO_RELOC);
     }
-  else if (TC_S_IS_BADPROC (fixP->fx_addsy))
-    {
-      as_bad (_("Looks like a proc, but can't tell what kind.\n"));
-    }				/* switch on proc type */
-
-  /* else Symbol is neither a sysproc nor a leafproc */
-  return 0;
 }
 
-/*****************************************************************************
-   s_leafproc:	process .leafproc pseudo-op
+/* s_leafproc:	process .leafproc pseudo-op
 
   	.leafproc takes two arguments, the second one is optional:
   		arg[1]: name of 'call' entry point to leaf procedure
@@ -2571,39 +2208,33 @@ reloc_callj (fixP)
 
   	If there are 2 distinct arguments, we must make sure that the 'bal'
   	entry point immediately follows the 'call' entry point in the linked
-  	list of symbols.
+  	list of symbols.  */
 
-  *************************************************************************** */
 static void
-s_leafproc (n_ops, args)
-     int n_ops;			/* Number of operands */
-     char *args[];		/* args[1]->1st operand, args[2]->2nd operand */
+s_leafproc (int n_ops,		/* Number of operands.  */
+	    char *args[])	/* args[1]->1st operand, args[2]->2nd operand.  */
 {
-  symbolS *callP;		/* Pointer to leafproc 'call' entry point symbol */
-  symbolS *balP;		/* Pointer to leafproc 'bal' entry point symbol */
+  symbolS *callP;		/* Pointer to leafproc 'call' entry point symbol.  */
+  symbolS *balP;		/* Pointer to leafproc 'bal' entry point symbol.  */
 
   if ((n_ops != 1) && (n_ops != 2))
     {
       as_bad (_("should have 1 or 2 operands"));
       return;
-    }				/* Check number of arguments */
+    }
 
   /* Find or create symbol for 'call' entry point.  */
   callP = symbol_find_or_make (args[1]);
 
   if (TC_S_IS_CALLNAME (callP))
-    {
-      as_warn (_("Redefining leafproc %s"), S_GET_NAME (callP));
-    }				/* is leafproc */
+    as_warn (_("Redefining leafproc %s"), S_GET_NAME (callP));
 
   /* If that was the only argument, use it as the 'bal' entry point.
-     * Otherwise, mark it as the 'call' entry point and find or create
-     * another symbol for the 'bal' entry point.
-   */
+     Otherwise, mark it as the 'call' entry point and find or create
+     another symbol for the 'bal' entry point.  */
   if ((n_ops == 1) || !strcmp (args[1], args[2]))
     {
       TC_S_FORCE_TO_BALNAME (callP);
-
     }
   else
     {
@@ -2611,32 +2242,30 @@ s_leafproc (n_ops, args)
 
       balP = symbol_find_or_make (args[2]);
       if (TC_S_IS_CALLNAME (balP))
-	{
-	  as_warn (_("Redefining leafproc %s"), S_GET_NAME (balP));
-	}
+	as_warn (_("Redefining leafproc %s"), S_GET_NAME (balP));
+
       TC_S_FORCE_TO_BALNAME (balP);
 
 #ifndef OBJ_ELF
       tc_set_bal_of_call (callP, balP);
 #endif
-    }				/* if only one arg, or the args are the same */
+    }
 }
 
-/*
-   s_sysproc: process .sysproc pseudo-op
+/* s_sysproc: process .sysproc pseudo-op
+
+   .sysproc takes two arguments:
+     arg[1]: name of entry point to system procedure
+     arg[2]: 'entry_num' (index) of system procedure in the range
+     [0,31] inclusive.
 
-        .sysproc takes two arguments:
-                arg[1]: name of entry point to system procedure
-                arg[2]: 'entry_num' (index) of system procedure in the range
-                        [0,31] inclusive.
+   For [ab].out, we store the 'entrynum' in the 'n_other' field of
+   the symbol.  Since that entry is normally 0, we bias 'entrynum'
+   by adding 1 to it.  It must be unbiased before it is used.  */
 
-        For [ab].out, we store the 'entrynum' in the 'n_other' field of
-        the symbol.  Since that entry is normally 0, we bias 'entrynum'
-        by adding 1 to it.  It must be unbiased before it is used.  */
 static void
-s_sysproc (n_ops, args)
-     int n_ops;			/* Number of operands */
-     char *args[];		/* args[1]->1st operand, args[2]->2nd operand */
+s_sysproc (int n_ops,		/* Number of operands.  */
+	   char *args[])	/* args[1]->1st operand, args[2]->2nd operand.  */
 {
   expressionS exp;
   symbolS *symP;
@@ -2645,7 +2274,7 @@ s_sysproc (n_ops, args)
     {
       as_bad (_("should have two operands"));
       return;
-    }				/* bad arg count */
+    }
 
   /* Parse "entry_num" argument and check it for validity.  */
   parse_expr (args[2], &exp);
@@ -2657,127 +2286,130 @@ s_sysproc (n_ops, args)
       return;
     }
 
-  /* Find/make symbol and stick entry number (biased by +1) into it */
+  /* Find/make symbol and stick entry number (biased by +1) into it.  */
   symP = symbol_find_or_make (args[1]);
 
   if (TC_S_IS_SYSPROC (symP))
-    {
-      as_warn (_("Redefining entrynum for sysproc %s"), S_GET_NAME (symP));
-    }				/* redefining */
+    as_warn (_("Redefining entrynum for sysproc %s"), S_GET_NAME (symP));
 
-  TC_S_SET_SYSPROC (symP, offs (exp));	/* encode entry number */
+  TC_S_SET_SYSPROC (symP, offs (exp));	/* Encode entry number.  */
   TC_S_FORCE_TO_SYSPROC (symP);
 }
 
-/*****************************************************************************
-   shift_ok:
-  	Determine if a "shlo" instruction can be used to implement a "ldconst".
-  	This means that some number X < 32 can be shifted left to produce the
-  	constant of interest.
+/* parse_po:	parse machine-dependent pseudo-op
 
-  	Return the shift count, or 0 if we can't do it.
-  	Caller calculates X by shifting original constant right 'shift' places.
+   This is a top-level routine for machine-dependent pseudo-ops.  It slurps
+   up the rest of the input line, breaks out the individual arguments,
+   and dispatches them to the correct handler.  */
 
-  *************************************************************************** */
-static int
-shift_ok (n)
-     int n;			/* The constant of interest */
+static void
+parse_po (int po_num)	/* Pseudo-op number:  currently S_LEAFPROC or S_SYSPROC.  */
 {
-  int shift;			/* The shift count */
+  /* Pointers operands, with no embedded whitespace.
+     arg[0] unused, arg[1-3]->operands.  */
+  char *args[4];
+  int n_ops;			/* Number of operands.  */
+  char *p;			/* Pointer to beginning of unparsed argument string.  */
+  char eol;			/* Character that indicated end of line.  */
 
-  if (n <= 0)
-    {
-      /* Can't do it for negative numbers */
-      return 0;
-    }
+  extern char is_end_of_line[];
 
-  /* Shift 'n' right until a 1 is about to be lost */
-  for (shift = 0; (n & 1) == 0; shift++)
-    {
-      n >>= 1;
-    }
+  /* Advance input pointer to end of line.  */
+  p = input_line_pointer;
+  while (!is_end_of_line[(unsigned char) *input_line_pointer])
+    input_line_pointer++;
 
-  if (n >= 32)
+  eol = *input_line_pointer;	/* Save end-of-line char.  */
+  *input_line_pointer = '\0';	/* Terminate argument list.  */
+
+  /* Parse out operands.  */
+  n_ops = get_args (p, args);
+  if (n_ops == -1)
+    return;
+
+  /* Dispatch to correct handler.  */
+  switch (po_num)
     {
-      return 0;
+    case S_SYSPROC:
+      s_sysproc (n_ops, args);
+      break;
+    case S_LEAFPROC:
+      s_leafproc (n_ops, args);
+      break;
+    default:
+      BAD_CASE (po_num);
+      break;
     }
-  return shift;
+
+  /* Restore eol, so line numbers get updated correctly.  Base
+     assembler assumes we leave input pointer pointing at char
+     following the eol.  */
+  *input_line_pointer++ = eol;
 }
 
-/* syntax: issue syntax error */
+/* reloc_callj:	Relocate a 'callj' instruction
 
-static void
-syntax ()
-{
-  as_bad (_("syntax error"));
-}				/* syntax() */
+  	This is a "non-(GNU)-standard" machine-dependent hook.  The base
+  	assembler calls it when it decides it can relocate an address at
+  	assembly time instead of emitting a relocation directive.
 
-/* targ_has_sfr:
+  	Check to see if the relocation involves a 'callj' instruction to a:
+  	    sysproc:	Replace the default 'call' instruction with a 'calls'
+  	    leafproc:	Replace the default 'call' instruction with a 'bal'.
+  	    other proc:	Do nothing.
 
-   Return TRUE iff the target architecture supports the specified
-   special-function register (sfr).  */
+  	See b.out.h for details on the 'n_other' field in a symbol structure.
 
-static int
-targ_has_sfr (n)
-     int n;			/* Number (0-31) of sfr */
+   IMPORTANT!:
+  	Assumes the caller has already figured out, in the case of a leafproc,
+  	to use the 'bal' entry point, and has substituted that symbol into the
+  	passed fixup structure.  */
+
+int
+reloc_callj (fixS *fixP)  /* Relocation that can be done at assembly time.  */    
 {
-  switch (architecture)
-    {
-    case ARCH_KA:
-    case ARCH_KB:
-    case ARCH_MC:
-    case ARCH_JX:
-      return 0;
-    case ARCH_HX:
-      return ((0 <= n) && (n <= 4));
-    case ARCH_CA:
-    default:
-      return ((0 <= n) && (n <= 2));
-    }
-}
+  /* Points to the binary for the instruction being relocated.  */
+  char *where;
 
-/* targ_has_iclass:
+  if (!fixP->fx_tcbit)
+    /* This wasn't a callj instruction in the first place.  */
+    return 0;
 
-   Return TRUE iff the target architecture supports the indicated
-   class of instructions.  */
-static int
-targ_has_iclass (ic)
-     /* Instruction class;  one of:
-        I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM, I_CX2, I_HX, I_HX2
-      */
-     int ic;
-{
-  iclasses_seen |= ic;
-  switch (architecture)
+  where = fixP->fx_frag->fr_literal + fixP->fx_where;
+
+  if (TC_S_IS_SYSPROC (fixP->fx_addsy))
     {
-    case ARCH_KA:
-      return ic & (I_BASE | I_KX);
-    case ARCH_KB:
-      return ic & (I_BASE | I_KX | I_FP | I_DEC);
-    case ARCH_MC:
-      return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL);
-    case ARCH_CA:
-      return ic & (I_BASE | I_CX | I_CX2 | I_CASIM);
-    case ARCH_JX:
-      return ic & (I_BASE | I_CX2 | I_JX);
-    case ARCH_HX:
-      return ic & (I_BASE | I_CX2 | I_JX | I_HX);
-    default:
-      if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL))
-	  && (iclasses_seen & (I_CX | I_CX2)))
-	{
-	  as_warn (_("architecture of opcode conflicts with that of earlier instruction(s)"));
-	  iclasses_seen &= ~ic;
-	}
-      return 1;
+      /* Symbol is a .sysproc: replace 'call' with 'calls'.  System
+         procedure number is (other-1).  */
+      md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4);
+
+      /* Nothing else needs to be done for this instruction.  Make
+         sure 'md_number_to_field()' will perform a no-op.  */
+      fixP->fx_bit_fixP = (bit_fixS *) 1;
+    }
+  else if (TC_S_IS_CALLNAME (fixP->fx_addsy))
+    {
+      /* Should not happen: see block comment above.  */
+      as_fatal (_("Trying to 'bal' to %s"), S_GET_NAME (fixP->fx_addsy));
+    }
+  else if (TC_S_IS_BALNAME (fixP->fx_addsy))
+    {
+      /* Replace 'call' with 'bal'; both instructions have the same
+         format, so calling code should complete relocation as if
+         nothing happened here.  */
+      md_number_to_chars (where, BAL, 4);
     }
+  else if (TC_S_IS_BADPROC (fixP->fx_addsy))
+    as_bad (_("Looks like a proc, but can't tell what kind.\n"));
+
+  /* Otherwise Symbol is neither a sysproc nor a leafproc.  */
+  return 0;
 }
 
 /* Handle the MRI .endian pseudo-op.  */
 
 static void
-s_endian (ignore)
-     int ignore ATTRIBUTE_UNUSED;
+s_endian (int ignore ATTRIBUTE_UNUSED)
 {
   char *name;
   char c;
@@ -2799,8 +2431,7 @@ s_endian (ignore)
 /* We have no need to default values of symbols.  */
 
 symbolS *
-md_undefined_symbol (name)
-     char *name ATTRIBUTE_UNUSED;
+md_undefined_symbol (char *name ATTRIBUTE_UNUSED)
 {
   return 0;
 }
@@ -2809,17 +2440,15 @@ md_undefined_symbol (name)
    On the i960, they're relative to the address of the instruction,
    which we have set up as the address of the fixup too.  */
 long
-md_pcrel_from (fixP)
-     fixS *fixP;
+md_pcrel_from (fixS *fixP)
 {
   return fixP->fx_where + fixP->fx_frag->fr_address;
 }
 
 void
-md_apply_fix3 (fixP, valP, seg)
-     fixS *fixP;
-     valueT *valP;
-     segT seg ATTRIBUTE_UNUSED;
+md_apply_fix3 (fixS *fixP,
+	       valueT *valP,
+	       segT seg ATTRIBUTE_UNUSED)
 {
   long val = *valP;
   char *place = fixP->fx_where + fixP->fx_frag->fr_literal;
@@ -2858,10 +2487,9 @@ md_apply_fix3 (fixP, valP, seg)
 
 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
 void
-tc_bout_fix_to_chars (where, fixP, segment_address_in_file)
-     char *where;
-     fixS *fixP;
-     relax_addressT segment_address_in_file;
+tc_bout_fix_to_chars (char *where,
+		      fixS *fixP,
+		      relax_addressT segment_address_in_file)
 {
   static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
   struct relocation_info ri;
@@ -2920,8 +2548,7 @@ tc_bout_fix_to_chars (where, fixP, segment_address_in_file)
 
 #if defined (OBJ_COFF) && defined (BFD)
 short
-tc_coff_fix2rtype (fixP)
-     fixS *fixP;
+tc_coff_fix2rtype (fixS *fixP)
 {
   if (fixP->fx_bsr)
     abort ();
@@ -2937,8 +2564,7 @@ tc_coff_fix2rtype (fixP)
 }
 
 int
-tc_coff_sizemachdep (frag)
-     fragS *frag;
+tc_coff_sizemachdep (fragS *frag)
 {
   if (frag->fr_next)
     return frag->fr_next->fr_address - frag->fr_address;
@@ -2948,12 +2574,13 @@ tc_coff_sizemachdep (frag)
 #endif
 
 /* Align an address by rounding it up to the specified boundary.  */
+
 valueT
-md_section_align (seg, addr)
-     segT seg;
-     valueT addr;		/* Address to be rounded up */
+md_section_align (segT seg,
+		  valueT addr)		/* Address to be rounded up.  */
 {
   int align;
+
 #ifdef BFD_ASSEMBLER
   align = bfd_get_section_alignment (stdoutput, seg);
 #else
@@ -2966,8 +2593,7 @@ extern int coff_flags;
 
 #ifdef OBJ_COFF
 void
-tc_headers_hook (headers)
-     object_headers *headers;
+tc_headers_hook (object_headers *headers)
 {
   switch (architecture)
     {
@@ -3048,8 +2674,7 @@ tc_headers_hook (headers)
    contains the bal entry point.  The bal symbol becomes a label.  */
 
 void
-tc_crawl_symbol_chain (headers)
-     object_headers *headers ATTRIBUTE_UNUSED;
+tc_crawl_symbol_chain (object_headers *headers ATTRIBUTE_UNUSED)
 {
   symbolS *symbolP;
 
@@ -3058,27 +2683,24 @@ tc_crawl_symbol_chain (headers)
 #ifdef OBJ_COFF
       if (TC_S_IS_SYSPROC (symbolP))
 	{
-	  /* second aux entry already contains the sysproc number */
+	  /* Second aux entry already contains the sysproc number.  */
 	  S_SET_NUMBER_AUXILIARY (symbolP, 2);
 	  S_SET_STORAGE_CLASS (symbolP, C_SCALL);
 	  S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
 	  continue;
-	}			/* rewrite sysproc */
+	}
 #endif /* OBJ_COFF */
 
       if (!TC_S_IS_BALNAME (symbolP) && !TC_S_IS_CALLNAME (symbolP))
-	{
-	  continue;
-	}			/* Not a leafproc symbol */
+	continue;
 
       if (!S_IS_DEFINED (symbolP))
-	{
-	  as_bad (_("leafproc symbol '%s' undefined"), S_GET_NAME (symbolP));
-	}			/* undefined leaf */
+	as_bad (_("leafproc symbol '%s' undefined"), S_GET_NAME (symbolP));
 
       if (TC_S_IS_CALLNAME (symbolP))
 	{
 	  symbolS *balP = tc_get_bal_of_call (symbolP);
+
 	  if (S_IS_EXTERNAL (symbolP) != S_IS_EXTERNAL (balP))
 	    {
 	      S_SET_EXTERNAL (symbolP);
@@ -3106,9 +2728,8 @@ tc_crawl_symbol_chain (headers)
 #endif
 
 void
-tc_set_bal_of_call (callP, balP)
-     symbolS *callP ATTRIBUTE_UNUSED;
-     symbolS *balP ATTRIBUTE_UNUSED;
+tc_set_bal_of_call (symbolS *callP ATTRIBUTE_UNUSED,
+		    symbolS *balP ATTRIBUTE_UNUSED)
 {
   know (TC_S_IS_CALLNAME (callP));
   know (TC_S_IS_BALNAME (balP));
@@ -3122,8 +2743,7 @@ tc_set_bal_of_call (callP, balP)
 #ifdef OBJ_ABOUT
 
   /* If the 'bal' entry doesn't immediately follow the 'call'
-     * symbol, unlink it from the symbol list and re-insert it.
-   */
+     symbol, unlink it from the symbol list and re-insert it.  */
   if (symbol_next (callP) != balP)
     {
       symbol_remove (balP, &symbol_rootP, &symbol_lastP);
@@ -3137,8 +2757,7 @@ tc_set_bal_of_call (callP, balP)
 }
 
 symbolS *
-tc_get_bal_of_call (callP)
-     symbolS *callP ATTRIBUTE_UNUSED;
+tc_get_bal_of_call (symbolS *callP ATTRIBUTE_UNUSED)
 {
   symbolS *retval;
 
@@ -3156,12 +2775,11 @@ tc_get_bal_of_call (callP)
 
   know (TC_S_IS_BALNAME (retval));
   return retval;
-}				/* _tc_get_bal_of_call() */
+}
 
 #ifdef OBJ_COFF
 void
-tc_coff_symbol_emit_hook (symbolP)
-     symbolS *symbolP ATTRIBUTE_UNUSED;
+tc_coff_symbol_emit_hook (symbolS *symbolP ATTRIBUTE_UNUSED)
 {
   if (TC_S_IS_CALLNAME (symbolP))
     {
@@ -3173,25 +2791,22 @@ tc_coff_symbol_emit_hook (symbolP)
       else
 	S_SET_STORAGE_CLASS (symbolP, C_LEAFSTAT);
       S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
-      /* fix up the bal symbol */
+      /* Fix up the bal symbol.  */
       S_SET_STORAGE_CLASS (balP, C_LABEL);
-    }				/* only on calls */
+    }
 }
 #endif /* OBJ_COFF */
 
 void
-i960_handle_align (fragp)
-     fragS *fragp ATTRIBUTE_UNUSED;
+i960_handle_align (fragS *fragp ATTRIBUTE_UNUSED)
 {
   if (!linkrelax)
     return;
 
 #ifndef OBJ_BOUT
-
   as_bad (_("option --link-relax is only supported in b.out format"));
   linkrelax = 0;
   return;
-
 #else
 
   /* The text section "ends" with another alignment reloc, to which we
@@ -3207,15 +2822,12 @@ i960_handle_align (fragp)
 }
 
 int
-i960_validate_fix (fixP, this_segment_type)
-     fixS *fixP;
-     segT this_segment_type ATTRIBUTE_UNUSED;
+i960_validate_fix (fixS *fixP, segT this_segment_type ATTRIBUTE_UNUSED)
 {
   if (fixP->fx_tcbit && TC_S_IS_CALLNAME (fixP->fx_addsy))
     {
       /* Relocation should be done via the associated 'bal'
          entry point symbol.  */
-
       if (!TC_S_IS_BALNAME (tc_get_bal_of_call (fixP->fx_addsy)))
 	{
 	  as_bad_where (fixP->fx_file, fixP->fx_line,
@@ -3233,11 +2845,8 @@ i960_validate_fix (fixP, this_segment_type)
 
 /* From cgen.c:  */
 
-static short tc_bfd_fix2rtype PARAMS ((fixS *));
-
 static short
-tc_bfd_fix2rtype (fixP)
-     fixS *fixP;
+tc_bfd_fix2rtype (fixS *fixP)
 {
   if (fixP->fx_pcrel == 0 && fixP->fx_size == 4)
     return BFD_RELOC_32;
@@ -3255,19 +2864,17 @@ tc_bfd_fix2rtype (fixP)
    FIXME: To what extent can we get all relevant targets to use this?  */
 
 arelent *
-tc_gen_reloc (section, fixP)
-     asection *section ATTRIBUTE_UNUSED;
-     fixS *fixP;
+tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixP)
 {
   arelent * reloc;
 
-  reloc = (arelent *) xmalloc (sizeof (arelent));
+  reloc = xmalloc (sizeof (arelent));
 
-  /* HACK: Is this right? */
+  /* HACK: Is this right?  */
   fixP->fx_r_type = tc_bfd_fix2rtype (fixP);
 
   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
-  if (reloc->howto == (reloc_howto_type *) NULL)
+  if (reloc->howto == NULL)
     {
       as_bad_where (fixP->fx_file, fixP->fx_line,
 		    "internal error: can't export reloc type %d (`%s')",
@@ -3278,7 +2885,7 @@ tc_gen_reloc (section, fixP)
 
   assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
 
-  reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
+  reloc->sym_ptr_ptr = xmalloc (sizeof (asymbol *));
   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
   reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
   reloc->addend = fixP->fx_addnumber;
@@ -3290,4 +2897,16 @@ tc_gen_reloc (section, fixP)
 
 #endif /* BFD_ASSEMBLER */
 
-/* end of tc-i960.c */
+const pseudo_typeS md_pseudo_table[] =
+{
+  {"bss", s_lcomm, 1},
+  {"endian", s_endian, 0},
+  {"extended", float_cons, 't'},
+  {"leafproc", parse_po, S_LEAFPROC},
+  {"sysproc", parse_po, S_SYSPROC},
+
+  {"word", cons, 4},
+  {"quad", cons, 16},
+
+  {0, 0, 0}
+};