2000-09-15 Kazu Hirata <kazu@hxi.com>

	* config/tc-h8300.h: Fix formatting.
	* config/tc-h8500.c: Likewise.
	* config/tc-h8500.h: Likewise.
	* config/tc-hppa.h: Likewise.
	* config/tc-i370.h: Likewise.
	* config/tc-i386.h: Likewise.
	* config/tc-i860.c: Likewise.
	* config/tc-i860.h: Likewise.
	* config/tc-i960.h: Likewise.
	* config/tc-ia64.c: Likewise.
	* config/tc-ia64.h: Likewise.

1 files changed, 4 insertions, 35 deletions

diff --git a/gas/config/tc-i860.c b/gas/config/tc-i860.c
index 56cad24..9ffd4ee 100644
--- a/gas/config/tc-i860.c
+++ b/gas/config/tc-i860.c
@@ -29,14 +29,12 @@
 #include "opcode/i860.h"
 #include "elf/i860.h"
 
-
 /* Defined by default since this is primarily a SVR4/860 assembler.
    However, I'm trying to leave the door open for Intel syntax. Of course,
    if full support for anything other than SVR4 is done, then we should
    select this based on a command-line flag.  */
 #define SYNTAX_SVR4
 
-
 /* The opcode hash table.  */
 static struct hash_control *op_hash = NULL;
 
@@ -56,7 +54,6 @@ const char EXP_CHARS[] = "eE";
    As in 0f12.456 or 0d1.2345e12.  */
 const char FLT_CHARS[] = "rRsSfFdDxXpP";
 
-
 /* Register prefix.  */
 #ifdef SYNTAX_SVR4
 static const char reg_prefix = '%';
@@ -64,7 +61,6 @@ static const char reg_prefix = '%';
 static const char reg_prefix = 0;
 #endif
 
-
 struct i860_it
 {
   char *error;
@@ -84,7 +80,6 @@ static char last_expand;
 /* If true, then warn if any pseudo operations were expanded.  */
 static int target_warn_expand = 0;
 
-
 /* Prototypes.  */
 static void i860_process_insn	PARAMS ((char *));
 static void s_dual		PARAMS ((int));
@@ -97,7 +92,6 @@ static bfd_reloc_code_real_type obtain_reloc_for_imm16
 static void print_insn		PARAMS ((struct i860_it *));
 #endif
 
-
 const pseudo_typeS md_pseudo_table[] =
 {
 #ifdef OBJ_ELF
@@ -109,7 +103,6 @@ const pseudo_typeS md_pseudo_table[] =
   {NULL,      0,             0},
 };
 
-
 /* Dual-instruction mode handling.  */
 enum dual
 {
@@ -117,7 +110,6 @@ enum dual
 };
 static enum dual dual_mode = DUAL_OFF;
 
-
 /* Handle ".dual" directive.  */
 static void
 s_dual (ignore)
@@ -126,7 +118,6 @@ s_dual (ignore)
   dual_mode = DUAL_ON;
 }
 
-
 /* Handle ".enddual" directive.  */
 static void
 s_enddual (ignore)
@@ -135,7 +126,6 @@ s_enddual (ignore)
   dual_mode = DUAL_OFF;
 }
 
-
 /* Temporary register used when expanding assembler pseudo operations.  */
 static int atmp = 31;
 
@@ -170,7 +160,6 @@ s_atmp (ignore)
   demand_empty_rest_of_line ();
 }
 
-
 /* This function is called once, at assembler startup time.  It should
    set up all the tables and data structures that the MD part of the
    assembler will need.  */
@@ -212,7 +201,6 @@ md_begin ()
     as_fatal (_("Defective assembler.  No assembly attempted."));
 }
 
-
 /* This is the core of the machine-dependent assembler.  STR points to a
    machine dependent instruction.  This function emits the frags/bytes
    it assembles to.  */
@@ -390,7 +378,7 @@ md_assemble (str)
 			     the_insn.reloc);
 
 	  /* Despite the odd name, this is a scratch field.  We use
-	     it to encode operand type information.  */ 
+	     it to encode operand type information.  */
 	  fix->fx_addnumber = the_insn.fup;
 	}
       the_insn = pseudo[++i];
@@ -399,7 +387,6 @@ md_assemble (str)
 
 }
 
-
 /* Assemble the instruction pointed to by STR.  */
 static void
 i860_process_insn (str)
@@ -869,7 +856,6 @@ i860_process_insn (str)
   the_insn.opcode = opcode;
 }
 
-
 static int
 i860_get_expression (str)
      char *str;
@@ -894,7 +880,6 @@ i860_get_expression (str)
   return 0;
 }
 
-
 /* Turn a string in input_line_pointer into a floating point constant of
    type TYPE, and store the appropriate bytes in *LITP.  The number of
    LITTLENUMS emitted is stored in *SIZEP.  An error message is returned,
@@ -957,7 +942,6 @@ md_atof (type, litP, sizeP)
   return 0;
 }
 
-
 /* Write out in current endian mode.  */
 void
 md_number_to_chars (buf, val, n)
@@ -971,7 +955,6 @@ md_number_to_chars (buf, val, n)
     number_to_chars_littleendian (buf, val, n);
 }
 
-
 /* This should never be called for i860.  */
 void
 md_number_to_disp (buf, val, n)
@@ -982,7 +965,6 @@ md_number_to_disp (buf, val, n)
   as_fatal (_("md_number_to_disp\n"));
 }
 
-
 /* This should never be called for i860.  */
 void
 md_number_to_field (buf, val, fix)
@@ -993,7 +975,6 @@ md_number_to_field (buf, val, fix)
   as_fatal (_("i860_number_to_field\n"));
 }
 
-
 /* This should never be called for i860.  */
 int
 md_estimate_size_before_relax (fragP, segtype)
@@ -1003,7 +984,6 @@ md_estimate_size_before_relax (fragP, segtype)
   as_fatal (_("i860_estimate_size_before_relax\n"));
 }
 
-
 #ifdef DEBUG_I860
 static void
 print_insn (insn)
@@ -1031,7 +1011,6 @@ print_insn (insn)
 }
 #endif /* DEBUG_I860 */
 
-
 
 #ifdef OBJ_ELF
 CONST char *md_shortopts = "VQ:";
@@ -1039,7 +1018,6 @@ CONST char *md_shortopts = "VQ:";
 CONST char *md_shortopts = "";
 #endif
 
-
 #define OPTION_EB		(OPTION_MD_BASE + 0)
 #define OPTION_EL		(OPTION_MD_BASE + 1)
 #define OPTION_WARN_EXPAND	(OPTION_MD_BASE + 2)
@@ -1052,7 +1030,6 @@ struct option md_longopts[] = {
 };
 size_t md_longopts_size = sizeof (md_longopts);
 
-
 int
 md_parse_option (c, arg)
      int c;
@@ -1091,7 +1068,6 @@ md_parse_option (c, arg)
   return 1;
 }
 
-
 void
 md_show_usage (stream)
      FILE *stream;
@@ -1117,7 +1093,6 @@ md_undefined_symbol (name)
   return 0;
 }
 
-
 /* The i860 denotes auto-increment with '++'.  */
 void
 md_operand (exp)
@@ -1136,7 +1111,6 @@ md_operand (exp)
     }
 }
 
-
 /* Round up a section size to the appropriate boundary.  */
 valueT
 md_section_align (segment, size)
@@ -1147,7 +1121,6 @@ md_section_align (segment, size)
   return size;
 }
 
-
 /* On the i860, a PC-relative offset is relative to the address of the
    of the offset plus its size.  */
 long
@@ -1157,7 +1130,6 @@ md_pcrel_from (fixP)
   return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
 }
 
-
 /* Determine the relocation needed for non PC-relative 16-bit immediates.
    Also adjust the given immediate as necessary.  Finally, check that
    all constraints (such as alignment) are satisfied.   */
@@ -1167,7 +1139,7 @@ obtain_reloc_for_imm16 (fix, val)
      long *val;
 {
   valueT fup = fix->fx_addnumber;
-  bfd_reloc_code_real_type reloc;  
+  bfd_reloc_code_real_type reloc;
 
   if (fix->fx_pcrel)
     abort ();
@@ -1253,7 +1225,6 @@ obtain_reloc_for_imm16 (fix, val)
   return reloc;
 }
 
-
 /* Attempt to simplify or eliminate a fixup. To indicate that a fixup
    has been eliminated, set fix->fx_done. If fix->fx_addsy is non-NULL,
    we will have to generate a reloc entry.  */
@@ -1327,7 +1298,7 @@ md_apply_fix3 (fix, valuep, seg)
 	  fix->fx_r_type = BFD_RELOC_NONE;
 	  fix->fx_done = 1;
 	}
-    } 
+    }
   else if (fup & OP_IMM_BR16)
     {
       if (val & 0x3)
@@ -1375,7 +1346,7 @@ md_apply_fix3 (fix, valuep, seg)
     }
   else if (fup != OP_NONE)
     {
-      as_bad_where (fix->fx_file, fix->fx_line, 
+      as_bad_where (fix->fx_file, fix->fx_line,
 		    _("Unrecognized fix-up (0x%08x)"), fup);
       abort ();
     }
@@ -1401,7 +1372,6 @@ md_apply_fix3 (fix, valuep, seg)
   return 0;
 }
 
-
 /* Generate a machine dependent reloc from a fixup.  */
 arelent*
 tc_gen_reloc (section, fixp)
@@ -1425,4 +1395,3 @@ tc_gen_reloc (section, fixp)
     }
   return reloc;
 }
-