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| author | H.J. Lu <hjl.tools@gmail.com> | 2008-04-18 13:10:32 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2008-04-18 13:10:32 +0000 |
| commit | dae39accc2005cb456ad00d4369b3ccc482f6a7d (patch) | |
| tree | 618818e95dd66e934b57c21fce3c0c91bec9f28d /gas/config/tc-i386.c | |
| parent | 266df637a89fce6f2d0adbbee3361a2ea4f25af2 (diff) | |
| download | gdb-dae39accc2005cb456ad00d4369b3ccc482f6a7d.zip gdb-dae39accc2005cb456ad00d4369b3ccc482f6a7d.tar.gz gdb-dae39accc2005cb456ad00d4369b3ccc482f6a7d.tar.bz2 | |
gas/
2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
* config/tc-i386.c (build_modrm_byte): Swap REG and NDS for
FMA.
gas/testsuite/
2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/arch-10.d: Updated.
* gas/i386/avx.d: Likewise.
* gas/i386/avx-intel.d: Likewise.
* gas/i386/x86-64-arch-2.d: Likewise.
* gas/i386/x86-64-avx.d: Likewise.
* gas/i386/x86-64-avx-intel.d: Likewise.
opcodes/
2008-04-18 H.J. Lu <hongjiu.lu@intel.com>
* i386-dis.c (OP_VEX_FMA): New.
(OP_EX_VexImmW): Likewise.
(VexFMA): Likewise.
(Vex128FMA): Likewise.
(EXVexImmW): Likewise.
(get_vex_imm8): Likewise.
(OP_EX_VexReg): Likewise.
(vex_i4_done): Renamed to ...
(vex_w_done): This.
(prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps
and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on
FMA instructions.
(print_insn): Updated.
(OP_EX_VexW): Rewrite to swap register in VEX with EX.
(OP_REG_VexI4): Check invalid high registers.
Diffstat (limited to 'gas/config/tc-i386.c')
| -rw-r--r-- | gas/config/tc-i386.c | 30 |
1 files changed, 25 insertions, 5 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 2a5e79c..ceabbf7 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -5002,7 +5002,7 @@ build_modrm_byte (void) nds = dest - 1; /* There are 2 kinds of instructions: - 1. 5 operands: one immediate operand and 4 register + 1. 5 operands: one immediate operand and 4 register operands or 3 register operands plus 1 memory operand. It must have VexNDS and VexW0 or VexW1. The destination must be either XMM or YMM register. @@ -5013,8 +5013,6 @@ build_modrm_byte (void) && i.tm.opcode_modifier.vexnds && (operand_type_equal (&i.tm.operand_types[dest], ®xmm) || operand_type_equal (&i.tm.operand_types[dest], ®ymm)) - && (operand_type_equal (&i.tm.operand_types[nds], ®xmm) - || operand_type_equal (&i.tm.operand_types[nds], ®ymm)) && ((dest == 4 && i.imm_operands == 1 && i.types[0].bitfield.vex_imm4 @@ -5027,8 +5025,6 @@ build_modrm_byte (void) && i.tm.opcode_modifier.veximmext)))) abort (); - i.vex.register_specifier = i.op[nds].regs; - if (i.imm_operands == 0) { /* When there is no immediate operand, generate an 8bit @@ -5049,6 +5045,16 @@ build_modrm_byte (void) source = 1; reg = 0; } + + /* FMA swaps REG and NDS. */ + if (i.tm.cpu_flags.bitfield.cpufma) + { + unsigned int tmp; + tmp = reg; + reg = nds; + nds = tmp; + } + assert (operand_type_equal (&i.tm.operand_types[reg], ®xmm) || operand_type_equal (&i.tm.operand_types[reg], ®ymm)); @@ -5094,6 +5100,15 @@ build_modrm_byte (void) i.types[imm].bitfield.imm8 = 1; } + /* FMA swaps REG and NDS. */ + if (i.tm.cpu_flags.bitfield.cpufma) + { + unsigned int tmp; + tmp = reg; + reg = nds; + nds = tmp; + } + assert (operand_type_equal (&i.tm.operand_types[reg], ®xmm) || operand_type_equal (&i.tm.operand_types[reg], ®ymm)); @@ -5101,6 +5116,11 @@ build_modrm_byte (void) |= ((i.op[reg].regs->reg_num + ((i.op[reg].regs->reg_flags & RegRex) ? 8 : 0)) << 4); } + + assert (operand_type_equal (&i.tm.operand_types[nds], ®xmm) + || operand_type_equal (&i.tm.operand_types[nds], ®ymm)); + i.vex.register_specifier = i.op[nds].regs; + } else source = dest = 0; |