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| author | Jan Beulich <jbeulich@novell.com> | 2004-11-25 08:42:54 +0000 |
|---|---|---|
| committer | Jan Beulich <jbeulich@novell.com> | 2004-11-25 08:42:54 +0000 |
| commit | 37edbb65ad7d81f172315eadf4f66783d78c36a5 (patch) | |
| tree | 9113686b18a9275f5a46f1c0ecd9d38d2b7dcb64 /gas/config/tc-i386.c | |
| parent | ebd98106b23a4d1d64a492cf26977e66c32393ac (diff) | |
| download | gdb-37edbb65ad7d81f172315eadf4f66783d78c36a5.zip gdb-37edbb65ad7d81f172315eadf4f66783d78c36a5.tar.gz gdb-37edbb65ad7d81f172315eadf4f66783d78c36a5.tar.bz2 | |
gas/
2004-11-25 Jan Beulich <jbeulich@novell.com>
* config/tc-i386.c (optimize_imm): Adjust immediates to only those
permissible for the selected instruction suffix.
(process_suffix): For DefaultSize instructions, suppressing the
guessing of a 'q' suffix if the instruction doesn't support it is
pointless, because only an 'l' suffix can be guessed in this place.
gas/testsuite/
2004-11-25 Jan Beulich <jbeulich@novell.com>
* gas/i386/x86-64-inval.[sl]: Remove sahf/lahf.
include/opcode/
2004-11-25 Jan Beulich <jbeulich@novell.com>
* i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves
to/from test registers are illegal in 64-bit mode. Add missing
NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix
(previously one had to explicitly encode a rex64 prefix). Re-enable
lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings
support it there. Add cmpxchg16b as per Intel's 64-bit documentation.
Diffstat (limited to 'gas/config/tc-i386.c')
| -rw-r--r-- | gas/config/tc-i386.c | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 430a338..ebe9523 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -2362,9 +2362,6 @@ process_suffix (void) && (i.tm.opcode_modifier & No_sSuf)) { i.suffix = stackop_size; - if (i.suffix == QWORD_MNEM_SUFFIX - && (i.tm.opcode_modifier & No_qSuf)) - i.suffix = LONG_MNEM_SUFFIX; } else if (intel_syntax && !i.suffix @@ -2702,7 +2699,7 @@ finalize_imm () i.types[0] = overlap0; overlap1 = i.types[1] & i.tm.operand_types[1]; - if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32)) + if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32 | Imm64)) && overlap1 != Imm8 && overlap1 != Imm8S && overlap1 != Imm16 && overlap1 != Imm32S && overlap1 != Imm32 && overlap1 != Imm64) |