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| author | H.J. Lu <hjl.tools@gmail.com> | 2019-03-17 07:25:08 +0800 |
|---|---|---|
| committer | H.J. Lu <hjl.tools@gmail.com> | 2019-03-17 07:25:22 +0800 |
| commit | dd22218cf26fa5d8beade7266de391a28e63527b (patch) | |
| tree | 0f466caac1966f1a9b7af5675aba2440e428a7a0 /gas/config/tc-i386.c | |
| parent | ab42892fb7d265e72a85e918d4f5c6dfeee3fcd8 (diff) | |
| download | gdb-dd22218cf26fa5d8beade7266de391a28e63527b.zip gdb-dd22218cf26fa5d8beade7266de391a28e63527b.tar.gz gdb-dd22218cf26fa5d8beade7266de391a28e63527b.tar.bz2 | |
x86: Correctly optimize EVEX to 128-bit VEX/EVEX
We can optimize 512-bit EVEX to 128-bit EVEX encoding for upper 16
vector registers only when AVX512VL is enabled. We can't optimize
EVEX to 128-bit VEX encoding when AVX isn't enabled.
PR gas/24352
* config/tc-i386.c (optimize_encoding): Encode 512-bit EVEX
with 128-bit VEX encoding only when AVX is enabled and with
128-bit EVEX encoding only when AVX512VL is enabled.
* testsuite/gas/i386/i386.exp: Run PR gas/24352 tests.
* testsuite/gas/i386/optimize-6.s: New file.
* testsuite/gas/i386/optimize-6a.d: Likewise.
* testsuite/gas/i386/optimize-6b.d: Likewise.
* testsuite/gas/i386/optimize-6c.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-7.s: Likewise.
* testsuite/gas/i386/x86-64-optimize-7a.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-7b.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-7c.d: Likewise.
* testsuite/gas/i386/x86-64-optimize-2.d: Updated.
Diffstat (limited to 'gas/config/tc-i386.c')
| -rw-r--r-- | gas/config/tc-i386.c | 18 |
1 files changed, 13 insertions, 5 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 1b1b0a9..959fda2 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -3975,10 +3975,13 @@ optimize_encoding (void) && !i.rounding && is_evex_encoding (&i.tm) && (i.vec_encoding != vex_encoding_evex + || cpu_arch_flags.bitfield.cpuavx + || cpu_arch_isa_flags.bitfield.cpuavx + || cpu_arch_flags.bitfield.cpuavx512vl + || cpu_arch_isa_flags.bitfield.cpuavx512vl || i.tm.cpu_flags.bitfield.cpuavx512vl || (i.tm.operand_types[2].bitfield.zmmword - && i.types[2].bitfield.ymmword) - || cpu_arch_isa_flags.bitfield.cpuavx512vl))) + && i.types[2].bitfield.ymmword)))) && ((i.tm.base_opcode == 0x55 || i.tm.base_opcode == 0x6655 || i.tm.base_opcode == 0x66df @@ -4032,14 +4035,19 @@ optimize_encoding (void) */ if (is_evex_encoding (&i.tm)) { - if (i.vec_encoding == vex_encoding_evex) - i.tm.opcode_modifier.evex = EVEX128; - else + if (i.vec_encoding != vex_encoding_evex + && (cpu_arch_flags.bitfield.cpuavx + || cpu_arch_isa_flags.bitfield.cpuavx)) { i.tm.opcode_modifier.vex = VEX128; i.tm.opcode_modifier.vexw = VEXW0; i.tm.opcode_modifier.evex = 0; } + else if (cpu_arch_flags.bitfield.cpuavx512vl + || cpu_arch_isa_flags.bitfield.cpuavx512vl) + i.tm.opcode_modifier.evex = EVEX128; + else + return; } else if (i.tm.operand_types[0].bitfield.regmask) { |