Remove trailing spaces in gas

1 files changed, 56 insertions, 56 deletions

diff --git a/gas/config/tc-crx.c b/gas/config/tc-crx.c
index a2314b7..0acb05e 100644
--- a/gas/config/tc-crx.c
+++ b/gas/config/tc-crx.c
@@ -57,7 +57,7 @@ typedef enum
     OP_NOT_EVEN,	/* Operand is Odd number, should be even.  */
     OP_ILLEGAL_DISPU4,	/* Operand is not within DISPU4 range.  */
     OP_ILLEGAL_CST4,	/* Operand is not within CST4 range.  */
-    OP_NOT_UPPER_64KB	/* Operand is not within the upper 64KB 
+    OP_NOT_UPPER_64KB	/* Operand is not within the upper 64KB
 			   (0xFFFF0000-0xFFFFFFFF).  */
   }
 op_err;
@@ -533,7 +533,7 @@ md_begin (void)
   /* Set up a hash table for the instructions.  */
   if ((crx_inst_hash = hash_new ()) == NULL)
     as_fatal (_("Virtual memory exhausted"));
-  
+
   while (crx_instruction[i].mnemonic != NULL)
     {
       const char *mnemonic = crx_instruction[i].mnemonic;
@@ -597,7 +597,7 @@ md_begin (void)
   linkrelax = 1;
 }
 
-/* Process constants (immediate/absolute) 
+/* Process constants (immediate/absolute)
    and labels (jump targets/Memory locations).  */
 
 static void
@@ -610,7 +610,7 @@ process_label_constant (char *str, ins * crx_ins)
   input_line_pointer = str;
 
   expression (&crx_ins->exp);
-  
+
   switch (crx_ins->exp.X_op)
     {
     case O_big:
@@ -651,7 +651,7 @@ process_label_constant (char *str, ins * crx_ins)
 	case arg_idxr:
 	    crx_ins->rtype = BFD_RELOC_CRX_REGREL22;
 	  break;
-	
+
 	case arg_c:
           if (IS_INSN_MNEMONIC ("bal") || IS_INSN_TYPE (DCR_BRANCH_INS))
 	    crx_ins->rtype = BFD_RELOC_CRX_REL16;
@@ -665,7 +665,7 @@ process_label_constant (char *str, ins * crx_ins)
           else if (IS_INSN_TYPE (CMPBR_INS) || IS_INSN_TYPE (COP_BRANCH_INS))
 	    crx_ins->rtype = BFD_RELOC_CRX_REL8_CMP;
 	  break;
-	
+
 	case arg_ic:
           if (IS_INSN_TYPE (ARITH_INS))
 	    crx_ins->rtype = BFD_RELOC_CRX_IMM32;
@@ -733,7 +733,7 @@ set_operand (char *operand, ins * crx_ins)
     case arg_c:	    /* Case 0x18.  */
       /* Set constant.  */
       process_label_constant (operandS, crx_ins);
-      
+
       if (cur_arg->type != arg_ic)
 	cur_arg->type = arg_c;
       break;
@@ -746,7 +746,7 @@ set_operand (char *operand, ins * crx_ins)
 	operandE++;
       *operandE = '\0';
       process_label_constant (operandS, crx_ins);
-      operandS = operandE;    
+      operandS = operandE;
     case arg_rbase: /* Case (r1).  */
       operandS++;
       /* Set register base.  */
@@ -768,7 +768,7 @@ set_operand (char *operand, ins * crx_ins)
       *operandE = '\0';
       process_label_constant (operandS, crx_ins);
       operandS = ++operandE;
-      
+
       /* Set register base.  */
       while ((*operandE != ',') && (! ISSPACE (*operandE)))
 	operandE++;
@@ -885,7 +885,7 @@ parse_operand (char *operand, ins * crx_ins)
     default:
 	break;
     }
-      
+
   if (strchr (operand, '(') != NULL)
     {
       if (strchr (operand, ',') != NULL
@@ -904,7 +904,7 @@ set_params:
   set_operand (operand, crx_ins);
 }
 
-/* Parse the various operands. Each operand is then analyzed to fillup 
+/* Parse the various operands. Each operand is then analyzed to fillup
    the fields in the crx_ins data structure.  */
 
 static void
@@ -999,18 +999,18 @@ gettrap (const char *s)
   return 0;
 }
 
-/* Post-Increment instructions, as well as Store-Immediate instructions, are a 
-   sub-group within load/stor instruction groups. 
-   Therefore, when parsing a Post-Increment/Store-Immediate insn, we have to 
-   advance the instruction pointer to the start of that sub-group (that is, up 
+/* Post-Increment instructions, as well as Store-Immediate instructions, are a
+   sub-group within load/stor instruction groups.
+   Therefore, when parsing a Post-Increment/Store-Immediate insn, we have to
+   advance the instruction pointer to the start of that sub-group (that is, up
    to the first instruction of that type).
    Otherwise, the insn will be mistakenly identified as of type LD_STOR_INS.  */
 
 static void
 handle_LoadStor (const char *operands)
 {
-  /* Post-Increment instructions precede Store-Immediate instructions in 
-     CRX instruction table, hence they are handled before. 
+  /* Post-Increment instructions precede Store-Immediate instructions in
+     CRX instruction table, hence they are handled before.
      This synchronization should be kept.  */
 
   /* Assuming Post-Increment insn has the following format :
@@ -1220,8 +1220,8 @@ print_constant (int nbits, int shift, argument *arg)
 	  break;
 	}
 
-      /* When instruction size is 3 and 'shift' is 16, a 16-bit constant is 
-	 always filling the upper part of output_opcode[1]. If we mistakenly 
+      /* When instruction size is 3 and 'shift' is 16, a 16-bit constant is
+	 always filling the upper part of output_opcode[1]. If we mistakenly
 	 write it to output_opcode[0], the constant prefix (that is, 'match')
 	 will be overridden.
 		 0	   1	     2	       3
@@ -1316,8 +1316,8 @@ get_number_of_operands (void)
   return i;
 }
 
-/* Verify that the number NUM can be represented in BITS bits (that is, 
-   within its permitted range), based on the instruction's FLAGS.  
+/* Verify that the number NUM can be represented in BITS bits (that is,
+   within its permitted range), based on the instruction's FLAGS.
    If UPDATE is nonzero, update the value of NUM if necessary.
    Return OP_LEGAL upon success, actual error type upon failure.  */
 
@@ -1379,11 +1379,11 @@ check_range (long *num, int bits, int unsigned flags, int update)
     {
       int is_dispu4 = 0;
 
-      uint32_t mul = (instruction->flags & DISPUB4 ? 1 
+      uint32_t mul = (instruction->flags & DISPUB4 ? 1
 		      : instruction->flags & DISPUW4 ? 2
 		      : instruction->flags & DISPUD4 ? 4
 		      : 0);
-      
+
       for (bin = 0; bin < cst4_maps; bin++)
 	{
 	  if (value == mul * bin)
@@ -1436,7 +1436,7 @@ check_range (long *num, int bits, int unsigned flags, int update)
 
 /* Assemble a single instruction:
    INSN is already parsed (that is, all operand values and types are set).
-   For instruction to be assembled, we need to find an appropriate template in 
+   For instruction to be assembled, we need to find an appropriate template in
    the instruction table, meeting the following conditions:
     1: Has the same number of operands.
     2: Has the same operand types.
@@ -1489,7 +1489,7 @@ assemble_insn (char *mnemonic, ins *insn)
   /* In some case, same mnemonic can appear with different instruction types.
      For example, 'storb' is supported with 3 different types :
      LD_STOR_INS, LD_STOR_INS_INC, STOR_IMM_INS.
-     We assume that when reaching this point, the instruction type was 
+     We assume that when reaching this point, the instruction type was
      pre-determined. We need to make sure that the type stays the same
      during a search for matching instruction.  */
   ins_type = CRX_INS_TYPE(instruction->flags);
@@ -1529,19 +1529,19 @@ assemble_insn (char *mnemonic, ins *insn)
 	{
 	  /* Reverse the operand indices for certain opcodes:
 	     Index 0	  -->> 1
-	     Index 1	  -->> 0	
+	     Index 1	  -->> 0
 	     Other index  -->> stays the same.  */
-	  int j = instruction->flags & REVERSE_MATCH ? 
-		  i == 0 ? 1 : 
-		  i == 1 ? 0 : i : 
+	  int j = instruction->flags & REVERSE_MATCH ?
+		  i == 0 ? 1 :
+		  i == 1 ? 0 : i :
 		  i;
 
-	  /* Only check range - don't update the constant's value, since the 
-	     current instruction may not be the last we try to match.  
-	     The constant's value will be updated later, right before printing 
+	  /* Only check range - don't update the constant's value, since the
+	     current instruction may not be the last we try to match.
+	     The constant's value will be updated later, right before printing
 	     it to the object file.  */
-  	  if ((insn->arg[j].X_op == O_constant) 
-	       && (op_error = check_range (&insn->arg[j].constant, cur_size[j], 
+  	  if ((insn->arg[j].X_op == O_constant)
+	       && (op_error = check_range (&insn->arg[j].constant, cur_size[j],
 					   cur_flags[j], 0)))
   	    {
 	      if (invalid_const == -1)
@@ -1551,10 +1551,10 @@ assemble_insn (char *mnemonic, ins *insn)
 	      }
 	      goto next_insn;
 	    }
-	  /* For symbols, we make sure the relocation size (which was already 
+	  /* For symbols, we make sure the relocation size (which was already
 	     determined) is sufficient.  */
 	  else if ((insn->arg[j].X_op == O_symbol)
-		    && ((bfd_reloc_type_lookup (stdoutput, insn->rtype))->bitsize 
+		    && ((bfd_reloc_type_lookup (stdoutput, insn->rtype))->bitsize
 			 > cur_size[j]))
 		  goto next_insn;
 	}
@@ -1593,7 +1593,7 @@ next_insn:
 	  as_bad (_("Invalid CST4 operand value (arg %d)"), invalid_const);
 	  break;
 	case OP_NOT_UPPER_64KB:
-	  as_bad (_("Operand value is not within upper 64 KB (arg %d)"), 
+	  as_bad (_("Operand value is not within upper 64 KB (arg %d)"),
 		    invalid_const);
 	  break;
 	default:
@@ -1601,7 +1601,7 @@ next_insn:
 	  break;
 	}
       }
-      
+
       return 0;
     }
   else
@@ -1610,23 +1610,23 @@ next_insn:
       /* Make further checkings (such that couldn't be made earlier).
 	 Warn the user if necessary.  */
       warn_if_needed (insn);
-      
+
       /* Check whether we need to adjust the instruction pointer.  */
       if (adjust_if_needed (insn))
-	/* If instruction pointer was adjusted, we need to update 
+	/* If instruction pointer was adjusted, we need to update
 	   the size of the current template operands.  */
 	GET_CURRENT_SIZE;
 
       for (i = 0; i < insn->nargs; i++)
         {
-	  int j = instruction->flags & REVERSE_MATCH ? 
-		  i == 0 ? 1 : 
-		  i == 1 ? 0 : i : 
+	  int j = instruction->flags & REVERSE_MATCH ?
+		  i == 0 ? 1 :
+		  i == 1 ? 0 : i :
 		  i;
 
 	  /* This time, update constant value before printing it.  */
-  	  if ((insn->arg[j].X_op == O_constant) 
-	       && (check_range (&insn->arg[j].constant, cur_size[j], 
+  	  if ((insn->arg[j].X_op == O_constant)
+	       && (check_range (&insn->arg[j].constant, cur_size[j],
 				cur_flags[j], 1) != OP_LEGAL))
 	      as_fatal (_("Illegal operand (arg %d)"), j+1);
 	}
@@ -1637,7 +1637,7 @@ next_insn:
       for (i = 0; i < insn->nargs; i++)
         {
 	  cur_arg_num = i;
-          print_operand (cur_size[i], instruction->operands[i].shift, 
+          print_operand (cur_size[i], instruction->operands[i].shift,
 			 &insn->arg[i]);
         }
     }
@@ -1651,15 +1651,15 @@ next_insn:
 void
 warn_if_needed (ins *insn)
 {
-  /* If the post-increment address mode is used and the load/store 
-     source register is the same as rbase, the result of the 
+  /* If the post-increment address mode is used and the load/store
+     source register is the same as rbase, the result of the
      instruction is undefined.  */
   if (IS_INSN_TYPE (LD_STOR_INS_INC))
     {
       /* Enough to verify that one of the arguments is a simple reg.  */
       if ((insn->arg[0].type == arg_r) || (insn->arg[1].type == arg_r))
 	if (insn->arg[0].r == insn->arg[1].r)
-	  as_bad (_("Same src/dest register is used (`r%d'), result is undefined"), 
+	  as_bad (_("Same src/dest register is used (`r%d'), result is undefined"),
 		   insn->arg[0].r);
     }
 
@@ -1671,17 +1671,17 @@ warn_if_needed (ins *insn)
 	as_bad (_("`%s' has undefined result"), ins_parse);
     }
 
-  /* If the rptr register is specified as one of the registers to be loaded, 
+  /* If the rptr register is specified as one of the registers to be loaded,
      the final contents of rptr are undefined. Thus, we issue an error.  */
   if (instruction->flags & NO_RPTR)
     {
       if ((1 << getreg_image (insn->arg[0].r)) & insn->arg[1].constant)
-	as_bad (_("Same src/dest register is used (`r%d'), result is undefined"), 
+	as_bad (_("Same src/dest register is used (`r%d'), result is undefined"),
 	 getreg_image (insn->arg[0].r));
     }
 }
 
-/* In some cases, we need to adjust the instruction pointer although a 
+/* In some cases, we need to adjust the instruction pointer although a
    match was already found. Here, we gather all these cases.
    Returns 1 if instruction pointer was adjusted, otherwise 0.  */
 
@@ -1705,7 +1705,7 @@ adjust_if_needed (ins *insn)
         }
     }
 
-  /* Optimization: Omit a zero displacement in bit operations, 
+  /* Optimization: Omit a zero displacement in bit operations,
      saving 2-byte encoding space (e.g., 'cbitw $8, 0(r1)').  */
   if (IS_INSN_TYPE (CSTBIT_INS))
     {
@@ -1792,7 +1792,7 @@ preprocess_reglist (char *param, int *allocated)
         {
           if (((cr = get_copregister (reg_name)) == nullcopregister)
 	      || (crx_copregtab[cr-MAX_REG].type != CRX_CS_REGTYPE))
-	    as_fatal (_("Illegal register `%s' in cop-special-register list"), 
+	    as_fatal (_("Illegal register `%s' in cop-special-register list"),
 		      reg_name);
 	  mask_reg (getreg_image (cr - cs0), &mask);
         }
@@ -1812,8 +1812,8 @@ preprocess_reglist (char *param, int *allocated)
           else if (((r = get_register (reg_name)) == nullregister)
 	      || (crx_regtab[r].type != CRX_U_REGTYPE))
 	    as_fatal (_("Illegal register `%s' in user register list"), reg_name);
-	  
-	  mask_reg (getreg_image (r - u0), &mask);	  
+
+	  mask_reg (getreg_image (r - u0), &mask);
 	}
       /* General purpose register r<N>.  */
       else