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author | Eric B. Weddington <eric.weddington@atmel.com> | 2011-03-22 18:10:48 +0000 |
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committer | Eric B. Weddington <eric.weddington@atmel.com> | 2011-03-22 18:10:48 +0000 |
commit | 8cc66334fa03f92b70da1a17685a093b6b0850ba (patch) | |
tree | 3c347ee26f7d734336dbf0c44bbffdc0af9ccd7a /gas/config/tc-avr.c | |
parent | 3167638f1e8e74e15650adda08449c2e32572552 (diff) | |
download | gdb-8cc66334fa03f92b70da1a17685a093b6b0850ba.zip gdb-8cc66334fa03f92b70da1a17685a093b6b0850ba.tar.gz gdb-8cc66334fa03f92b70da1a17685a093b6b0850ba.tar.bz2 |
/bfd:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* archures.c: Add AVR XMEGA architecture information.
* cpu-avr.c (arch_info_struct): Likewise.
* elf32-avr.c (bfd_elf_avr_final_write_processing): Likewise.
(elf32_avr_object_p): Likewise.
/gas:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* config/tc-avr.c (struct avr_opcodes_s): Add opcode field.
(AVR_INSN): Change definition to match.
(avr_opcodes): Likewise, change to match.
(mcu_types): Add XMEGA architecture names and new XMEGA device names.
(md_show_usage): Add XMEGA architecture names.
(avr_operand): Add 'E' constraint for DES instruction of XMEGA devices.
Add support for SPM Z+ instruction.
* doc/c-avr.texi: Add documentation for XMEGA architectures and
devices.
/include/opcode:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA):
New instruction set flags.
(AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA.
/ld:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* Makefile.am (ALL_EMULATION_SOURCES): Add AVR XMEGA architectures.
(eavrxmega?.c): Likewise.
* configure.tgt (targ_extra_emuls): Likewise.
* emulparams/avrxmega1.sh: New file.
* emulparams/avrxmega2.sh: Likewise.
* emulparams/avrxmega3.sh: Likewise.
* emulparams/avrxmega4.sh: Likewise.
* emulparams/avrxmega5.sh: Likewise.
* emulparams/avrxmega6.sh: Likewise.
* emulparams/avrxmega7.sh: Likewise.
* emultempl/avrelf.em (avr_elf_${EMULATION_NAME}_before_allocation):
Add avrxmega6, avrxmega7 to list of architectures for no stubs.
/opcodes:
2011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
* avr-dis.c (avr_operand): Add opcode_str parameter. Check for
post-increment to support LPM Z+ instruction. Add support for 'E'
constraint for DES instruction.
(print_insn_avr): Adjust calls to avr_operand. Rename variable.
Diffstat (limited to 'gas/config/tc-avr.c')
-rw-r--r-- | gas/config/tc-avr.c | 49 |
1 files changed, 46 insertions, 3 deletions
diff --git a/gas/config/tc-avr.c b/gas/config/tc-avr.c index 4214d61..e924939 100644 --- a/gas/config/tc-avr.c +++ b/gas/config/tc-avr.c @@ -29,18 +29,19 @@ struct avr_opcodes_s { char * name; char * constraints; + char * opcode; int insn_size; /* In words. */ int isa; unsigned int bin_opcode; }; #define AVR_INSN(NAME, CONSTR, OPCODE, SIZE, ISA, BIN) \ -{#NAME, CONSTR, SIZE, ISA, BIN}, +{#NAME, CONSTR, OPCODE, SIZE, ISA, BIN}, struct avr_opcodes_s avr_opcodes[] = { #include "opcode/avr.h" - {NULL, NULL, 0, 0, 0} + {NULL, NULL, NULL, 0, 0, 0} }; const char comment_chars[] = ";"; @@ -79,6 +80,13 @@ static struct mcu_type_s mcu_types[] = {"avr5", AVR_ISA_AVR51, bfd_mach_avr5}, {"avr51", AVR_ISA_AVR51, bfd_mach_avr51}, {"avr6", AVR_ISA_AVR6, bfd_mach_avr6}, + {"avrxmega1", AVR_ISA_XMEGA, bfd_mach_avrxmega1}, + {"avrxmega2", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, + {"avrxmega3", AVR_ISA_XMEGA, bfd_mach_avrxmega3}, + {"avrxmega4", AVR_ISA_XMEGA, bfd_mach_avrxmega4}, + {"avrxmega5", AVR_ISA_XMEGA, bfd_mach_avrxmega5}, + {"avrxmega6", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, + {"avrxmega7", AVR_ISA_XMEGA, bfd_mach_avrxmega7}, {"at90s1200", AVR_ISA_1200, bfd_mach_avr1}, {"attiny11", AVR_ISA_AVR1, bfd_mach_avr1}, {"attiny12", AVR_ISA_AVR1, bfd_mach_avr1}, @@ -237,6 +245,21 @@ static struct mcu_type_s mcu_types[] = {"at90usb1287",AVR_ISA_AVR51, bfd_mach_avr51}, {"atmega2560", AVR_ISA_AVR6, bfd_mach_avr6}, {"atmega2561", AVR_ISA_AVR6, bfd_mach_avr6}, + {"atxmega16a4", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, + {"atxmega16d4", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, + {"atxmega32a4", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, + {"atxmega32d4", AVR_ISA_XMEGA, bfd_mach_avrxmega2}, + {"atxmega64a3", AVR_ISA_XMEGA, bfd_mach_avrxmega4}, + {"atxmega64d3", AVR_ISA_XMEGA, bfd_mach_avrxmega4}, + {"atxmega64a1", AVR_ISA_XMEGA, bfd_mach_avrxmega5}, + {"atxmega128a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, + {"atxmega128d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, + {"atxmega192a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, + {"atxmega192d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, + {"atxmega256a3", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, + {"atxmega256a3b",AVR_ISA_XMEGA, bfd_mach_avrxmega6}, + {"atxmega256d3", AVR_ISA_XMEGA, bfd_mach_avrxmega6}, + {"atxmega128a1", AVR_ISA_XMEGA, bfd_mach_avrxmega7}, {NULL, 0, 0} }; @@ -413,6 +436,11 @@ md_show_usage (FILE *stream) " avr5 - enhanced AVR core with up to 64K program memory\n" " avr51 - enhanced AVR core with up to 128K program memory\n" " avr6 - enhanced AVR core with up to 256K program memory\n" + " avrxmega3 - XMEGA, > 8K, <= 64K FLASH, > 64K RAM\n" + " avrxmega4 - XMEGA, > 64K, <= 128K FLASH, <= 64K RAM\n" + " avrxmega5 - XMEGA, > 64K, <= 128K FLASH, > 64K RAM\n" + " avrxmega6 - XMEGA, > 128K, <= 256K FLASH, <= 64K RAM\n" + " avrxmega7 - XMEGA, > 128K, <= 256K FLASH, > 64K RAM\n" " or immediate microcontroller name.\n")); fprintf (stream, _(" -mall-opcodes accept all AVR opcodes, even if not supported by MCU\n" @@ -840,7 +868,12 @@ avr_operand (struct avr_opcodes_s *opcode, if (*str == '+') { ++str; - op_mask |= 1; + char *s; + for (s = opcode->opcode; *s; ++s) + { + if (*s == '+') + op_mask |= (1 << (15 - (s - opcode->opcode))); + } } /* attiny26 can do "lpm" and "lpm r,Z" but not "lpm r,Z+". */ @@ -957,6 +990,16 @@ avr_operand (struct avr_opcodes_s *opcode, } break; + case 'E': + { + unsigned int x; + + x = avr_get_constant (str, 15); + str = input_line_pointer; + op_mask |= (x << 4); + } + break; + case '?': break; |