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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2019-09-24 10:18:12 +0100 |
|---|---|---|
| committer | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2019-09-24 10:29:18 +0100 |
| commit | e449ea97ebd3c11a8da5df174f1a1333fbe82828 (patch) | |
| tree | 46fc427d8e83e925202e427d2a631dc9c3bcf480 /gas/config/tc-arm.c | |
| parent | 5d33705c7befb0711c134089cc8fffdbf9bc031c (diff) | |
| download | gdb-e449ea97ebd3c11a8da5df174f1a1333fbe82828.zip gdb-e449ea97ebd3c11a8da5df174f1a1333fbe82828.tar.gz gdb-e449ea97ebd3c11a8da5df174f1a1333fbe82828.tar.bz2 | |
[ARM]: Modify assembler to accept floating and signless datatypes for MVE instruction VLDR.
This patch modifies assembler to accept the equivalent sized floating
and signless datatypes for VLDR instruction but as alias for the unsigned version.
gas/ChangeLog:
2019-09-23 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
* config/tc-arm.c (do_mve_vstr_vldr_RQ): Modify function to allow float
* and signless datatypes for few cases of VLDR instruction.
* testsuite/gas/arm/mve-vldr-bad-3.l: Modify.
* testsuite/gas/arm/mve-vldr-bad-3.s: Likewise.
* testsuite/gas/arm/mve-vstrldr-1.d: Likewise.
* testsuite/gas/arm/mve-vstrldr-1.s: Likewise.
Diffstat (limited to 'gas/config/tc-arm.c')
| -rw-r--r-- | gas/config/tc-arm.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 7760d18..2f394ba 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -17282,6 +17282,7 @@ static void do_mve_vstr_vldr_RQ (int size, int elsize, int load) { unsigned os = inst.operands[1].imm >> 5; + unsigned type = inst.vectype.el[0].type; constraint (os != 0 && size == 8, _("can not shift offsets when accessing less than half-word")); constraint (os && os != neon_logbits (size), @@ -17312,15 +17313,14 @@ do_mve_vstr_vldr_RQ (int size, int elsize, int load) constraint (inst.operands[0].reg == (inst.operands[1].imm & 0x1f), _("destination register and offset register may not be" " the same")); - constraint (size == elsize && inst.vectype.el[0].type != NT_unsigned, + constraint (size == elsize && type == NT_signed, BAD_EL_TYPE); + constraint (size != elsize && type != NT_unsigned && type != NT_signed, BAD_EL_TYPE); - constraint (inst.vectype.el[0].type != NT_unsigned - && inst.vectype.el[0].type != NT_signed, BAD_EL_TYPE); - inst.instruction |= (inst.vectype.el[0].type == NT_unsigned) << 28; + inst.instruction |= ((size == elsize) || (type == NT_unsigned)) << 28; } else { - constraint (inst.vectype.el[0].type != NT_untyped, BAD_EL_TYPE); + constraint (type != NT_untyped, BAD_EL_TYPE); } inst.instruction |= 1 << 23; |