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authorMatthew Gretton-Dann <matthew.gretton-dann@arm.com>2010-09-17 10:13:41 +0000
committerMatthew Gretton-Dann <matthew.gretton-dann@arm.com>2010-09-17 10:13:41 +0000
commitdb472d6ff0f438a21b357249a9b48e4b74498076 (patch)
tree89e4361f9af8995b4b1a3375bc119da4dd9ecb03 /gas/config/tc-arm.c
parent8f8067050f5b34b2fb72d810d98206918281b67c (diff)
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2010-09-17 Tejas Belagod <tejas.belagod@arm.com>
* config/tc-arm.c (insns): Change MRC entry to accept APSR_RR instead of just RR. 2010-09-17 Tejas Belagod <tejas.belagod@arm.com> * gas/arm/copro.s: Add test for APSR_nzcv as a MRC operand. * gas/arm/copro.d: Change pc in MRC to disassemble as APSR_nzcv. Also add disassembly for test added in copro.s 2010-09-17 Tejas Belagod <tejas.belagod@arm.com> * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
Diffstat (limited to 'gas/config/tc-arm.c')
-rw-r--r--gas/config/tc-arm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index f1ffe9c..cebf2df 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -16704,7 +16704,7 @@ static const struct asm_opcode insns[] =
TCE("stc", c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
TC3("stcl", c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
TCE("mcr", e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
- TCE("mrc", e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
+ TCE("mrc", e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
#undef ARM_VARIANT
#define ARM_VARIANT & arm_ext_v2s /* ARM 3 - swp instructions. */