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| author | Matthew Gretton-Dann <matthew.gretton-dann@arm.com> | 2012-08-24 08:03:39 +0000 |
|---|---|---|
| committer | Matthew Gretton-Dann <matthew.gretton-dann@arm.com> | 2012-08-24 08:03:39 +0000 |
| commit | 9eb6c0f132631312886f7084d96448e46a053fb8 (patch) | |
| tree | 003aba8f43552c1b6ada1389ea3ee863e0858fa5 /gas/config/tc-arm.c | |
| parent | 8884b7208b371aa604ceab383380956c687065ee (diff) | |
| download | gdb-9eb6c0f132631312886f7084d96448e46a053fb8.zip gdb-9eb6c0f132631312886f7084d96448e46a053fb8.tar.gz gdb-9eb6c0f132631312886f7084d96448e46a053fb8.tar.bz2 | |
* gas/config/tc-arm.c (do_rm_rn): New function.
(do_strlex): Likewise.
(do_t_strlex): Likewise.
(insns): Add support for LDRA/STRL instructions.
* gas/testsuite/gas/arm/armv8-a-bad.l: Update testcase.
* gas/testsuite/gas/arm/armv8-a-bad.s: Likewise.
* gas/testsuite/gas/arm/armv8-a.d: Likewise.
* gas/testsuite/gas/arm/armv8-a.s: Likewise.
* opcodes/arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
(thumb32_opcodes): Likewise.
(print_arm_insn): Add support for %<>T formatter.
Diffstat (limited to 'gas/config/tc-arm.c')
| -rw-r--r-- | gas/config/tc-arm.c | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index d98944b..93542e3 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -7383,6 +7383,13 @@ do_rd_rm (void) } static void +do_rm_rn (void) +{ + inst.instruction |= inst.operands[0].reg; + inst.instruction |= inst.operands[1].reg << 16; +} + +static void do_rd_rn (void) { inst.instruction |= inst.operands[0].reg << 12; @@ -8729,6 +8736,25 @@ do_strexd (void) inst.instruction |= inst.operands[3].reg << 16; } +/* ARM V8 STRL. */ +static void +do_strlex (void) +{ + constraint (inst.operands[0].reg == inst.operands[1].reg + || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); + + do_rd_rm_rn (); +} + +static void +do_t_strlex (void) +{ + constraint (inst.operands[0].reg == inst.operands[1].reg + || inst.operands[0].reg == inst.operands[2].reg, BAD_OVERLAP); + + do_rm_rd_rn (); +} + /* ARM V6 SXTAH extracts a 16-bit value from a register, sign extends it to 32-bits, and adds the result to a value in another register. You can specify a rotation by 0, 8, 16, or 24 bits @@ -17991,6 +18017,25 @@ static const struct asm_opcode insns[] = tCE("sevl", 320f005, _sevl, 0, (), noargs, t_hint), TUE("hlt", 1000070, ba80, 1, (oIffffb), bkpt, t_hlt), + TCE("ldraex", 1900e9f, e8d00fef, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), + TCE("ldraexd", 1b00e9f, e8d000ff, 3, (RRnpc, oRRnpc, RRnpcb), + ldrexd, t_ldrexd), + TCE("ldraexb", 1d00e9f, e8d00fcf, 2, (RRnpc,RRnpcb), rd_rn, rd_rn), + TCE("ldraexh", 1f00e9f, e8d00fdf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), + TCE("strlex", 1800e90, e8c00fe0, 3, (RRnpc, RRnpc, RRnpcb), + strlex, t_strlex), + TCE("strlexd", 1a00e90, e8c000f0, 4, (RRnpc, RRnpc, oRRnpc, RRnpcb), + strexd, t_strexd), + TCE("strlexb", 1c00e90, e8c00fc0, 3, (RRnpc, RRnpc, RRnpcb), + strlex, t_strlex), + TCE("strlexh", 1e00e90, e8c00fd0, 3, (RRnpc, RRnpc, RRnpcb), + strlex, t_strlex), + TCE("ldra", 1900c9f, e8d00faf, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), + TCE("ldrab", 1d00c9f, e8d00f8f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), + TCE("ldrah", 1f00c9f, e8d00f9f, 2, (RRnpc, RRnpcb), rd_rn, rd_rn), + TCE("strl", 180fc90, e8c00faf, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), + TCE("strlb", 1c0fc90, e8c00f8f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), + TCE("strlh", 1e0fc90, e8c00f9f, 2, (RRnpc, RRnpcb), rm_rn, rd_rn), /* ARMv8 T32 only. */ #undef ARM_VARIANT |