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| author | Nick Clifton <nickc@redhat.com> | 2009-12-02 20:26:30 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2009-12-02 20:26:30 +0000 |
| commit | 03ee1b7f8eb5cee9654e9d789e0c46a098bed895 (patch) | |
| tree | 44760d80f8168eb6f7d0b59222cfaf3f584b1cd3 /gas/config/tc-arm.c | |
| parent | 8cebebb9a2f399f50f4284797528fb952dd80576 (diff) | |
| download | gdb-03ee1b7f8eb5cee9654e9d789e0c46a098bed895.zip gdb-03ee1b7f8eb5cee9654e9d789e0c46a098bed895.tar.gz gdb-03ee1b7f8eb5cee9654e9d789e0c46a098bed895.tar.bz2 | |
PR gas/11013
* arm-dis.c (thumb32_opc): Adjust disassembly of QADD, QDADD, QSUB
and QDSUB.
* gas/arm/arch7em.d: Update expected disassembly.
* gas/arm/thumb32.d: Likewise.
* config/tc-arm.c (do_t_simd2): New function.
(insns): Use do_t_simd2 for QADD, QDADD, QSUB and QDSUB.
Diffstat (limited to 'gas/config/tc-arm.c')
| -rw-r--r-- | gas/config/tc-arm.c | 26 |
1 files changed, 22 insertions, 4 deletions
diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 0ef05df..076c82b 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -11103,6 +11103,24 @@ do_t_simd (void) } static void +do_t_simd2 (void) +{ + unsigned Rd, Rn, Rm; + + Rd = inst.operands[0].reg; + Rm = inst.operands[1].reg; + Rn = inst.operands[2].reg; + + reject_bad_reg (Rd); + reject_bad_reg (Rn); + reject_bad_reg (Rm); + + inst.instruction |= Rd << 8; + inst.instruction |= Rn << 16; + inst.instruction |= Rm; +} + +static void do_t_smc (void) { unsigned int value = inst.reloc.exp.X_add_number; @@ -16494,10 +16512,10 @@ static const struct asm_opcode insns[] = TCE("smulwb", 12000a0, fb30f000, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), TCE("smulwt", 12000e0, fb30f010, 3, (RRnpc, RRnpc, RRnpc), smul, t_simd), - TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd), - TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd), - TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd), - TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd), + TCE("qadd", 1000050, fa80f080, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), + TCE("qdadd", 1400050, fa80f090, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), + TCE("qsub", 1200050, fa80f0a0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), + TCE("qdsub", 1600050, fa80f0b0, 3, (RRnpc, RRnpc, RRnpc), rd_rm_rn, t_simd2), #undef ARM_VARIANT #define ARM_VARIANT & arm_ext_v5e /* ARM Architecture 5TE. */ |