aarch64: Add support for +mops

This patch adds support for FEAT_MOPS, an Armv8.8-A extension
that provides memcpy and memset acceleration instructions.

I took the perhaps controversial decision to generate the individual
instruction forms using macros rather than list them out individually.
This becomes useful with a follow-on patch to check that code follows
the correct P/M/E sequence.
[https://developer.arm.com/documentation/ddi0596/2021-09/Base-Instructions?lang=en]

include/
	* opcode/aarch64.h (AARCH64_FEATURE_MOPS): New macro.
	(AARCH64_ARCH_V8_8): Make armv8.8-a imply AARCH64_FEATURE_MOPS.
	(AARCH64_OPND_MOPS_ADDR_Rd): New aarch64_opnd.
	(AARCH64_OPND_MOPS_ADDR_Rs): Likewise.
	(AARCH64_OPND_MOPS_WB_Rn): Likewise.

opcodes/
	* aarch64-asm.h (ins_x0_to_x30): New inserter.
	* aarch64-asm.c (aarch64_ins_x0_to_x30): New function.
	* aarch64-dis.h (ext_x0_to_x30): New extractor.
	* aarch64-dis.c (aarch64_ext_x0_to_x30): New function.
	* aarch64-tbl.h (aarch64_feature_mops): New feature set.
	(aarch64_feature_mops_memtag): Likewise.
	(MOPS, MOPS_MEMTAG, MOPS_INSN, MOPS_MEMTAG_INSN)
	(MOPS_CPY_OP1_OP2_PME_INSN, MOPS_CPY_OP1_OP2_INSN, MOPS_CPY_OP1_INSN)
	(MOPS_CPY_INSN, MOPS_SET_OP1_OP2_PME_INSN, MOPS_SET_OP1_OP2_INSN)
	(MOPS_SET_INSN): New macros.
	(aarch64_opcode_table): Add MOPS instructions.
	(aarch64_opcode_table): Add entries for AARCH64_OPND_MOPS_ADDR_Rd,
	AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn.
	* aarch64-opc.c (aarch64_print_operand): Handle
	AARCH64_OPND_MOPS_ADDR_Rd, AARCH64_OPND_MOPS_ADDR_Rs and
	AARCH64_OPND_MOPS_WB_Rn.
	(verify_three_different_regs): New function.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.

gas/
	* doc/c-aarch64.texi: Document +mops.
	* config/tc-aarch64.c (parse_x0_to_x30): New function.
	(parse_operands): Handle AARCH64_OPND_MOPS_ADDR_Rd,
	AARCH64_OPND_MOPS_ADDR_Rs and AARCH64_OPND_MOPS_WB_Rn.
	(aarch64_features): Add "mops".
	* testsuite/gas/aarch64/mops.s, testsuite/gas/aarch64/mops.d: New test.
	* testsuite/gas/aarch64/mops_invalid.s,
	* testsuite/gas/aarch64/mops_invalid.d,
	* testsuite/gas/aarch64/mops_invalid.l: Likewise.

1 files changed, 33 insertions, 0 deletions

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 2181fa1..4aadf5b 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -3918,6 +3918,22 @@ parse_sve_address (char **str, aarch64_opnd_info *operand,
 			     SHIFTED_MUL_VL);
 }
 
+/* Parse a register X0-X30.  The register must be 64-bit and register 31
+   is unallocated.  */
+static bool
+parse_x0_to_x30 (char **str, aarch64_opnd_info *operand)
+{
+  const reg_entry *reg = parse_reg (str);
+  if (!reg || !aarch64_check_reg_type (reg, REG_TYPE_R_64))
+    {
+      set_syntax_error (_(get_reg_expected_msg (REG_TYPE_R_64)));
+      return false;
+    }
+  operand->reg.regno = reg->number;
+  operand->qualifier = AARCH64_OPND_QLF_X;
+  return true;
+}
+
 /* Parse an operand for a MOVZ, MOVN or MOVK instruction.
    Return TRUE on success; otherwise return FALSE.  */
 static bool
@@ -7491,6 +7507,21 @@ parse_operands (char *str, const aarch64_opcode *opcode)
 	      break;
 	    }
 
+	case AARCH64_OPND_MOPS_ADDR_Rd:
+	case AARCH64_OPND_MOPS_ADDR_Rs:
+	  po_char_or_fail ('[');
+	  if (!parse_x0_to_x30 (&str, info))
+	    goto failure;
+	  po_char_or_fail (']');
+	  po_char_or_fail ('!');
+	  break;
+
+	case AARCH64_OPND_MOPS_WB_Rn:
+	  if (!parse_x0_to_x30 (&str, info))
+	    goto failure;
+	  po_char_or_fail ('!');
+	  break;
+
 	default:
 	  as_fatal (_("unhandled operand code %d"), operands[i]);
 	}
@@ -9929,6 +9960,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
 			AARCH64_ARCH_NONE},
   {"pauth",		AARCH64_FEATURE (AARCH64_FEATURE_PAC, 0),
 			AARCH64_ARCH_NONE},
+  {"mops",		AARCH64_FEATURE (AARCH64_FEATURE_MOPS, 0),
+			AARCH64_ARCH_NONE},
   {NULL,		AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
 };