AArch64: Update encodings for stg, st2g, stzg and st2zg.

This patch is part of a series of patches to introduce a few changes to the
Armv8.5-A Memory Tagging Extension. This patch updates the st*g instructions
to use a previously reserved field for a new register operand. Thus the
new versions of the instructions are as follows:

- STG Xt, [<Xn|SP>, #<simm>]
- STG Xt, [<Xn|SP>, #<simm>]!
- STG Xt, [<Xn|SP>], #<simm>
- STZG Xt, [<Xn|SP>, #<simm>]
- STZG Xt, [<Xn|SP>, #<simm>]!
- STZG Xt, [<Xn|SP>], #<simm>
- ST2G Xt, [<Xn|SP>, #<simm>]
- ST2G Xt, [<Xn|SP>, #<simm>]!
- ST2G Xt, [<Xn|SP>], #<simm>
- STZ2G Xt, [<Xn|SP>, #<simm>]
- STZ2G Xt, [<Xn|SP>, #<simm>]!
- STZ2G Xt, [<Xn|SP>], #<simm>

Committed on behalf of Sudakshina Das.

*** gas/ChangeLog ***

	* config/tc-aarch64.c (warn_unpredictable_ldst): Exempt
	stg, st2g, stzg and stz2g from Xt == Xn with writeback warning.
	* testsuite/gas/aarch64/armv8_5-a-memtag.d: Change tests for
	stg, stzg, st2g and stz2g.
	* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
	* testsuite/gas/aarch64/illegal-memtag.s: Likewise.

*** opcodes/ChangeLog ***

	* aarch64-tbl.h (QL_LDST_AT): Update macro.
	(aarch64_opcode): Change encoding for stg, stzg
	st2g and st2zg.
	* aarch64-asm-2.c: Regenerated.
	* aarch64-dis-2.c: Regenerated.
	* aarch64-opc-2.c: Regenerated.

1 files changed, 2 insertions, 0 deletions

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 537f00c..1acf6f6 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6772,6 +6772,8 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
 	   == AARCH64_OPND_CLASS_INT_REG)
 	  && opnds[0].reg.regno == opnds[1].addr.base_regno
 	  && opnds[1].addr.base_regno != REG_SP
+	  /* Exempt STG/STZG/ST2G/STZ2G.  */
+	  && !(opnds[1].type == AARCH64_OPND_ADDR_SIMM13)
 	  && opnds[1].addr.writeback)
 	as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
       break;