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authorIan Lance Taylor <ian@airs.com>1999-05-27 22:36:51 +0000
committerIan Lance Taylor <ian@airs.com>1999-05-27 22:36:51 +0000
commit6da466c730cb814a5903049a922e2169e60a311c (patch)
treee8f10a5f15ff41f530ca2e790ee5b24119cda940 /gas/config/m68k-parse.h
parent461d5ddde0734c3bf0420e475341e7e79418bc54 (diff)
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1999-05-28 Torbjorn Granlund <tege@matematik.su.se>
* config/tc-m68k.c (m68k_ip): Check for disallowed index register width for Coldfire. (arch_coldfire_p): New #define. (m68k_ip, m68k_init_after_args): Use arch_coldfire_p. 1999-05-28 Linus Nordberg <linus.nordberg@canit.se> * config/tc-m68k.c (install_operand): Add places `n', `o'. * config/tc-m68k.c (m68k_ip): Add formats `E', `G', `H'. (install_operand): Add place `N'. (init_table): Add registers ACC, MACSR, MASK. * config/m68k-parse.h (m68k_register): Add ACC, MACSR, MASK. * config/tc-m68k.c: Change mcf5200 --> mcf. (archs): Add mcf5206e, mcf5307. (m68k_ip): Add format `u'. (install_operand): Add place `m', `M', `h'. (init_table): Add upper/lower registers. * config/m68k-parse.h (m68k_register): Add upper/lower registers.
Diffstat (limited to 'gas/config/m68k-parse.h')
-rw-r--r--gas/config/m68k-parse.h44
1 files changed, 43 insertions, 1 deletions
diff --git a/gas/config/m68k-parse.h b/gas/config/m68k-parse.h
index e131342..cdb5f60 100644
--- a/gas/config/m68k-parse.h
+++ b/gas/config/m68k-parse.h
@@ -1,5 +1,6 @@
/* m68k-parse.h -- header file for m68k assembler
- Copyright (C) 1987, 91, 92, 93, 94, 1995 Free Software Foundation, Inc.
+ Copyright (C) 1987, 91, 92, 93, 94, 95, 96, 1999
+ Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
@@ -83,6 +84,9 @@ enum m68k_register
ZPC, /* Hack for Program space, but 0 addressing */
SR, /* Status Reg */
CCR, /* Condition code Reg */
+ ACC, /* Accumulator Reg */
+ MACSR, /* MAC Status Reg */
+ MASK, /* Modulus Reg */
/* These have to be grouped together for the movec instruction to work. */
USP, /* User Stack Pointer */
@@ -165,6 +169,44 @@ enum m68k_register
ZADDR5,
ZADDR6,
ZADDR7,
+
+ /* Upper and lower half of data and address registers. Order *must*
+ be DATAxL, ADDRxL, DATAxU, ADDRxU. */
+ DATA0L, /* lower half of data registers */
+ DATA1L,
+ DATA2L,
+ DATA3L,
+ DATA4L,
+ DATA5L,
+ DATA6L,
+ DATA7L,
+
+ ADDR0L, /* lower half of address registers */
+ ADDR1L,
+ ADDR2L,
+ ADDR3L,
+ ADDR4L,
+ ADDR5L,
+ ADDR6L,
+ ADDR7L,
+
+ DATA0U, /* upper half of data registers */
+ DATA1U,
+ DATA2U,
+ DATA3U,
+ DATA4U,
+ DATA5U,
+ DATA6U,
+ DATA7U,
+
+ ADDR0U, /* upper half of address registers */
+ ADDR1U,
+ ADDR2U,
+ ADDR3U,
+ ADDR4U,
+ ADDR5U,
+ ADDR6U,
+ ADDR7U,
};
/* Size information. */