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authorJie Zhang <jie.zhang@analog.com>2008-09-26 04:49:17 +0000
committerJie Zhang <jie.zhang@analog.com>2008-09-26 04:49:17 +0000
commit37b329352042564a5b4c41c1244fc04af8c3cb04 (patch)
tree125b4e701fe2d6fc7834ecfa267a8b9ea6acdeda /gas/config/bfin-parse.y
parent181b26eaf1ad521819d2ef3257cf172f0d1cf6b3 (diff)
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* config/bfin-parse.y (asm_1): Fix reduce/reduce conflicts.
Diffstat (limited to 'gas/config/bfin-parse.y')
-rw-r--r--gas/config/bfin-parse.y22
1 files changed, 10 insertions, 12 deletions
diff --git a/gas/config/bfin-parse.y b/gas/config/bfin-parse.y
index 283b813..f91224e 100644
--- a/gas/config/bfin-parse.y
+++ b/gas/config/bfin-parse.y
@@ -1932,22 +1932,20 @@ asm_1:
else
return yyerror ("Bad shift value or register");
}
- | HALF_REG ASSIGN HALF_REG LESS_LESS expr
- {
- if (IS_UIMM ($5, 4))
- {
- notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
- $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
- }
- else
- return yyerror ("Bad shift value");
- }
| HALF_REG ASSIGN HALF_REG LESS_LESS expr smod
{
if (IS_UIMM ($5, 4))
{
- notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
- $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
+ if ($6.s0)
+ {
+ notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4 (S)\n");
+ $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, $6.s0, HL2 ($1, $3));
+ }
+ else
+ {
+ notethat ("dsp32shiftimm: dregs_half = dregs_half << uimm4\n");
+ $$ = DSP32SHIFTIMM (0x0, &$1, imm5 ($5), &$3, 2, HL2 ($1, $3));
+ }
}
else
return yyerror ("Bad shift value");