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| author | Jie Zhang <jie.zhang@analog.com> | 2009-09-03 16:17:36 +0000 |
|---|---|---|
| committer | Jie Zhang <jie.zhang@analog.com> | 2009-09-03 16:17:36 +0000 |
| commit | c958a8a8fb341605fa49cb30d62e98f1b833f542 (patch) | |
| tree | 4842b85e37b23a13c68aa40ccaf409f9e10cdd18 /gas/config/bfin-defs.h | |
| parent | 1d3ad4d0b0eafa4c7182f41077b6bfa1d8bc53c8 (diff) | |
| download | gdb-c958a8a8fb341605fa49cb30d62e98f1b833f542.zip gdb-c958a8a8fb341605fa49cb30d62e98f1b833f542.tar.gz gdb-c958a8a8fb341605fa49cb30d62e98f1b833f542.tar.bz2 | |
gas/
* config/bfin-defs.h (IS_GENREG): Define.
(IS_DAGREG): Define.
(IS_SYSREG): Define.
* config/bfin-parse.y (asm_1): Check illegal register move
instructions.
gas/testsuite/
* gas/bfin/expected_move_errors.s,
gas/bfin/expected_move_errors.l: Add "LC1 = I0;".
* gas/bfin/move.s, gas/bfin/move.d: Remove "CYCLES = A0.W".
opcodes/
* bfin-dis.c (IS_DREG): Define.
(IS_PREG): Define.
(IS_AREG): Define.
(IS_GENREG): Define.
(IS_DAGREG): Define.
(IS_SYSREG): Define.
(decode_REGMV_0): Check illegal register move instructions.
Diffstat (limited to 'gas/config/bfin-defs.h')
| -rw-r--r-- | gas/config/bfin-defs.h | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/gas/config/bfin-defs.h b/gas/config/bfin-defs.h index 8923b73..8846a02 100644 --- a/gas/config/bfin-defs.h +++ b/gas/config/bfin-defs.h @@ -201,6 +201,25 @@ enum reg_class #define IS_CREG(r) ((r).regno == REG_LC0 || (r).regno == REG_LC1) #define IS_ALLREG(r) ((r).regno < T_NOGROUP) +#define IS_GENREG(r) \ + (IS_DREG (r) || IS_PREG (r) \ + || (r).regno == REG_A0x || (r).regno == REG_A0w \ + || (r).regno == REG_A1x || (r).regno == REG_A1w) + +#define IS_DAGREG(r) \ + (IS_IREG (r) || IS_MREG (r) || IS_BREG (r) || IS_LREG (r)) + +#define IS_SYSREG(r) \ + ((r).regno == REG_ASTAT || (r).regno == REG_SEQSTAT \ + || (r).regno == REG_SYSCFG || (r).regno == REG_RETI \ + || (r).regno == REG_RETX || (r).regno == REG_RETN \ + || (r).regno == REG_RETE || (r).regno == REG_RETS \ + || (r).regno == REG_LC0 || (r).regno == REG_LC1 \ + || (r).regno == REG_LT0 || (r).regno == REG_LT1 \ + || (r).regno == REG_LB0 || (r).regno == REG_LB1 \ + || (r).regno == REG_CYCLES || (r).regno == REG_CYCLES2 \ + || (r).regno == REG_EMUDAT) + /* Expression value macros. */ typedef enum |