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authorJan Beulich <jbeulich@suse.com>2020-01-03 10:16:44 +0100
committerJan Beulich <jbeulich@suse.com>2020-01-03 10:16:44 +0100
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parent567dfba2bed4bce68a13b0c8963dec9605dea6c8 (diff)
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Arm64: correct address index operands for LD1RO{H,W,D}
Just like their LD1RQ{H,W,D} counterparts, as per the specification the index registers get scaled by element size.
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2020-01-03 Jan Beulich <jbeulich@suse.com>
+ * testsuite/gas/aarch64/f64mm.s: Scale index of LD1RO{H,W,D}.
+ * testsuite/gas/aarch64/f64mm.d: Adjust expectations.
+
+2020-01-03 Jan Beulich <jbeulich@suse.com>
+
* testsuite/gas/aarch64/i8mm.s: Add 128-bit form tests for
by-element usdot. Add 64-bit form tests for by-element sudot.
* testsuite/gas/aarch64/i8mm.d: Adjust expectations.