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| author | Jan Beulich <jbeulich@novell.com> | 2017-11-15 08:51:03 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2017-11-15 08:51:03 +0100 |
| commit | 3a2430e05b1503653ae09cb21feb2a0d4ea51ec7 (patch) | |
| tree | 1ca884a972fcb08063cd9462d0d68556ecfacb6a /gas/ChangeLog | |
| parent | 0645f0a2a75ad77d9786595978591d3f302f9647 (diff) | |
| download | gdb-3a2430e05b1503653ae09cb21feb2a0d4ea51ec7.zip gdb-3a2430e05b1503653ae09cb21feb2a0d4ea51ec7.tar.gz gdb-3a2430e05b1503653ae09cb21feb2a0d4ea51ec7.tar.bz2 | |
x86: drop VEXI4_Fixup()
The low four bits of an immediate being set when the high bits specify a
fourth register operand is not a problem: CPUs ignore these bits rather
than raising #UD. Take care of incrementing codep in OP_EX_VexW()
instead.
Diffstat (limited to 'gas/ChangeLog')
| -rw-r--r-- | gas/ChangeLog | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 66bc034..3624da7 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,10 @@ 2017-11-15 Jan Beulich <jbeulich@suse.com> + * testsuite/gas/i386/noextreg.{s,d}: New. + * testsuite/gas/i386/i386.exp: Run new test. + +2017-11-15 Jan Beulich <jbeulich@suse.com> + * testsuite/gas/i386/x86-64-reg.s: Add extended byte reg tests. * testsuite/gas/i386/x86-64-reg.d, testsuite/gas/i386/x86-64-reg-intel.d, |