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authorThiemo Seufer <ths@networkno.de>2006-06-06 10:49:48 +0000
committerThiemo Seufer <ths@networkno.de>2006-06-06 10:49:48 +0000
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parent5cffb350132d39af2aac9598d2a14c9fde260cb5 (diff)
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[ gas/ChangeLog ]
* config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro. (CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete. (macro_build): Update comment. (mips_ip): Allow DSP64 instructions for MIPS64R2. (mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and CPU_HAS_MDMX. (mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and MIPS_CPU_ASE_MDMX flags for sb1. [ gas/testsuite/ChangeLog ] * gas/mips/mips64-dsp.s, gas/mips/mips64-dsp.d: New DSP64 tests. * gas/mips/mips.exp: Run DSP64 tests. [ opcodes/ChangeLog ] * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2. * mips-opc.c: Add DSP64 instructions.
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+++ b/gas/ChangeLog
@@ -1,3 +1,15 @@
+2006-06-06 Thiemo Seufer <ths@mips.com>
+ Chao-ying Fu <fu@mips.com>
+
+ * config/tc-mips.c (ISA_SUPPORTS_DSP64): New macro.
+ (CPU_HAS_MIPS3D, CPU_HAS_MDMX, CPU_HAS_DSP, CPU_HAS_MT): Delete.
+ (macro_build): Update comment.
+ (mips_ip): Allow DSP64 instructions for MIPS64R2.
+ (mips_after_parse_args): Remove uses of CPU_HAS_MIPS3D and
+ CPU_HAS_MDMX.
+ (mips_cpu_info): Fix formatting. Add MIPS_CPU_ASE_MIPS3D and
+ MIPS_CPU_ASE_MDMX flags for sb1.
+
2006-06-05 Thiemo Seufer <ths@mips.com>
* config/tc-mips.c (macro_build): Use INSERT_OPERAND wherew