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authorJan Beulich <jbeulich@suse.com>2021-03-25 08:18:41 +0100
committerJan Beulich <jbeulich@suse.com>2021-03-25 08:18:41 +0100
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x86: fix AMD Zen3 insns
For INVLPGB the operand count was wrong (besides %edx there's also %ecx which is an input to the insn). In this case I see little sense in retaining the bogus 2-operand template. Plus swapping of the operands wasn't properly suppressed for Intel syntax. For PVALIDATE, RMPADJUST, and RMPUPDATE bogus single operand templates were specified. These get retained, as the address operand is the only one really needed to expressed non-default address size, but only for compatibility reasons. Proper multi-operand insn get introduced and the testcases get adjusted / extended accordingly. While at it also drop the redundant definition of __amd64__ - we already have x86_64 defined (or not) to distinguish 64-bit and non-64-bit cases.
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2021-03-25 Jan Beulich <jbeulich@suse.com>
+ * config/tc-i386.c (md_assemble): Widen set of insns to avoid
+ swapping operands for.
+ * testsuite/gas/i386/invlpgb.s: Fix, re-arrange, and add Intel
+ syntax tests.
+ * testsuite/gas/i386/snp.s: Re-arrange and add multi-operand as
+ well as Intel syntax tests.
+ * testsuite/gas/i386/invlpgb.d, testsuite/gas/i386/snp.d: Adjust
+ expectations.
+ * testsuite/gas/i386/invlpgb64.d, testsuite/gas/i386/snp64.d:
+ Likewise. Drop passing --def-sym to as.
+
+2021-03-25 Jan Beulich <jbeulich@suse.com>
+
PR/gas 27419
* config/tc-i386.c (process_suffix): Restrict (%rip) -> (%eip)
conversion to x32 mode.