diff options
| author | Jan Beulich <jbeulich@suse.com> | 2020-02-14 14:27:28 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2020-02-14 14:27:28 +0100 |
| commit | 65fca0597f3a5f76f6d7d79bc3a922c160254e0a (patch) | |
| tree | 52ea7653991780e22ee475a6963e8d29a2fe72c6 /gas/ChangeLog | |
| parent | b6773884364e0275a793adad4b025913fa155d5a (diff) | |
| download | gdb-65fca0597f3a5f76f6d7d79bc3a922c160254e0a.zip gdb-65fca0597f3a5f76f6d7d79bc3a922c160254e0a.tar.gz gdb-65fca0597f3a5f76f6d7d79bc3a922c160254e0a.tar.bz2 | |
x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZX
For these to get treatment consistent with other operand size checking
the special logic shouldn't live in md_assemble(), but process_suffix().
And there's more logic involved than simply zapping the suffix.
Note however that MOVS[BW]* and MOVZ[BW]* still won't be fully
consistent, due to the objection to fold MOVS* templates just like was
done for MOVZ* in c07315e0c6 ("x86: allow suffix-less movzw and 64-bit
movzb").
Note further that it is against my own intentions to have MOVSX/MOVZX
silently default to a byte source in AT&T mode. This should happen only
when the destination register is a 16-bit one. In all other cases there
is an ambiguity, and the user should be warned. But it was explicitly
requested for this to be done in a way inconsistent with everything
else.
Note finally that the assembler change points out (and this patch fixes)
a wrong Intel syntax test introduced by bc31405ebb2c ("x86-64: Properly
encode and decode movsxd"): When source code specifies a 16-bit
destination register, disassembly expectations shouldn't have been to
find a 32-bit one.
Diffstat (limited to 'gas/ChangeLog')
| -rw-r--r-- | gas/ChangeLog | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog index 56d5071..39b1a38 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,33 @@ 2020-02-14 Jan Beulich <jbeulich@suse.com> + PR gas/25438 + * config/tc-i386.c (md_assemble): Move movsx/movzx special + casing ... + (process_suffix): ... here. Consider just the first operand + initially. + (check_long_reg): Drop opcode 0x63 special case again. + * testsuite/gas/i386/i386.s, testsuite/gas/i386/iamcu-1.s, + testsuite/gas/i386/ilp32/x86-64.s, testsuite/gas/i386/x86_64.s: + Move ambiguous operand size tests ... + * testsuite/gas/i386/noreg16.s, testsuite/gas/i386/noreg32.s, + testsuite/gas/i386/noreg64.s: ... here. + * testsuite/gas/i386/i386.d, testsuite/gas/i386/i386-intel.d + testsuite/gas/i386/iamcu-1.d, testsuite/gas/i386/ilp32/x86-64.d, + testsuite/gas/i386/k1om.d, testsuite/gas/i386/l1om.d, + testsuite/gas/i386/movx16.l, testsuite/gas/i386/movx32.l, + testsuite/gas/i386/movx64.l, testsuite/gas/i386/noreg16.d, + testsuite/gas/i386/noreg32.d, testsuite/gas/i386/noreg64.d, + testsuite/gas/i386/x86-64-movsxd.d, + testsuite/gas/i386/x86-64-movsxd-intel.d, + testsuite/gas/i386/x86_64.d, testsuite/gas/i386/x86_64-intel.d: + Adjust expectations. + * testsuite/gas/i386/movx16.s, testsuite/gas/i386/movx16.l, + testsuite/gas/i386/movx32.s, testsuite/gas/i386/movx32.l, + testsuite/gas/i386/movx64.s, testsuite/gas/i386/movx64.l: New. + * testsuite/gas/i386/i386.exp: Run new tests. + +2020-02-14 Jan Beulich <jbeulich@suse.com> + * config/tc-i386.c (process_operands): Also skip segment override prefix emission if it matches an already present one. * testsuite/gas/i386/prefix32.s: Add double segment override |