cpu,opcodes: add instruction semantics to bpf.cpu and minor fixes

This patch adds semantic RTL descriptions to the eBPF instructions
defined in cpu/bpf.cpu.  It also contains a couple of minor
improvements.

Tested in bpf-unknown-none targets.
No regressions.

cpu/ChangeLog:

2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
	    David Faust <david.faust@oracle.com>

	* bpf.cpu (define-alu-insn-un): Add definitions of semantics.
	(define-alu-insn-mov): Likewise.
	(daib): Likewise.
	(define-alu-instructions): Likewise.
	(define-endian-insn): Likewise.
	(define-lddw): Likewise.
	(dlabs): Likewise.
	(dlind): Likewise.
	(dxli): Likewise.
	(dxsi): Likewise.
	(dsti): Likewise.
	(define-ldstx-insns): Likewise.
	(define-st-insns): Likewise.
	(define-cond-jump-insn): Likewise.
	(dcji): Likewise.
	(define-condjump-insns): Likewise.
	(define-call-insn): Likewise.
	(ja): Likewise.
	("exit"): Likewise.
	(define-atomic-insns): Likewise.
	(sem-exchange-and-add): New macro.
	* bpf.cpu ("brkpt"): New instruction.
	(bpfbf): Set word-bitsize to 32 and insn-endian big.
	(h-gpr): Prefer r0 to `a' and r6 to `ctx'.
	(h-pc): Expand definition.
	* bpf.opc (bpf_print_insn): Set endian_code to BIG.

opcodes/ChangeLog:

2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
	    David Faust <david.faust@oracle.com>

	* bpf-desc.c: Regenerate.
	* bpf-opc.h: Likewise.
	* bpf-opc.c: Likewise.
	* bpf-dis.c: Likewise.

3 files changed, 272 insertions, 91 deletions

diff --git a/cpu/ChangeLog b/cpu/ChangeLog
index f791c00..30b884c 100644
--- a/cpu/ChangeLog
+++ b/cpu/ChangeLog
@@ -1,3 +1,33 @@
+2020-05-28  Jose E. Marchesi  <jose.marchesi@oracle.com>
+	    David Faust <david.faust@oracle.com>
+
+	* bpf.cpu (define-alu-insn-un): Add definitions of semantics.
+	(define-alu-insn-mov): Likewise.
+	(daib): Likewise.
+	(define-alu-instructions): Likewise.
+	(define-endian-insn): Likewise.
+	(define-lddw): Likewise.
+	(dlabs): Likewise.
+	(dlind): Likewise.
+	(dxli): Likewise.
+	(dxsi): Likewise.
+	(dsti): Likewise.
+	(define-ldstx-insns): Likewise.
+	(define-st-insns): Likewise.
+	(define-cond-jump-insn): Likewise.
+	(dcji): Likewise.
+	(define-condjump-insns): Likewise.
+	(define-call-insn): Likewise.
+	(ja): Likewise.
+	("exit"): Likewise.
+	(define-atomic-insns): Likewise.
+	(sem-exchange-and-add): New macro.
+	* bpf.cpu ("brkpt"): New instruction.
+	(bpfbf): Set word-bitsize to 32 and insn-endian big.
+	(h-gpr): Prefer r0 to `a' and r6 to `ctx'.
+	(h-pc): Expand definition.
+	* bpf.opc (bpf_print_insn): Set endian_code to BIG.
+
 2020-05-21  Alan Modra  <amodra@gmail.com>
 
 	* mep.opc (mep_cgen_expand_macros_and_parse_operand): Replace
diff --git a/cpu/bpf.cpu b/cpu/bpf.cpu
index 89a27fe..47d7cb0 100644
--- a/cpu/bpf.cpu
+++ b/cpu/bpf.cpu
@@ -32,6 +32,10 @@
   (name bpf)
   (comment "Linux kernel BPF")
   (insn-lsb0? #t)
+  ;; XXX explain the default-alignment setting is for the simulator.
+  ;; It is confusing that the simulator follows the emulated memory
+  ;; access conventions for fetching instructions by pieces...
+  (default-alignment unaligned)
   (machs bpf)
   (isas ebpfle ebpfbe))
 
@@ -121,7 +125,8 @@
 (define-cpu
   (name bpfbf)
   (comment "Linux kernel eBPF virtual CPU")
-  (word-bitsize 32))
+  (insn-endian big)
+  (word-bitsize 64))
 
 (define-mach
   (name bpf)
@@ -159,13 +164,19 @@
             (r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6)
             (r7 7) (r8 8) (r9 9) (fp 10)
             ;; Additional names recognized when assembling.
-            (a 0) (ctx 6) (r10 10))))
+            (r0 0) (r6 6) (r10 10))))
 
 ;; The program counter.  CGEN requires it, even if it is not visible
 ;; to eBPF programs.
 
-(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
-
+(define-hardware
+  (name h-pc)
+  (comment "program counter")
+  (attrs PC PROFILE all-isas)
+  (type pc UDI)
+  (get () (raw-reg h-pc))
+  (set (newval) (set (raw-reg h-pc) newval)))
+  
 ;; A 64-bit h-sint to be used by the imm64 operand below.  XXX this
 ;; shouldn't be needed, as h-sint is supposed to be able to hold
 ;; 64-bit values.  However, in practice CGEN limits h-sint to 32 bits
@@ -361,60 +372,101 @@
 ;;   ADD[32]{i,r}le for the little-endian ISA
 ;;   ADD[32]{i,r}be for the big-endian ISA
 ;;
-;; The `i' variants perform `src OP dst -> dst' operations.
-;; The `r' variants perform `dst OP imm32 -> dst' operations.
+;; The `i' variants perform `dst OP imm32 -> dst' operations.
+;; The `r' variants perform `dst OP src -> dst' operations.
 ;;
 ;; The variants with 32 in their name are of ALU class.  Otherwise
 ;; they are ALU64 class.
 
-(define-pmacro (define-alu-insn-un x-basename x-suffix x-op-class x-op-code x-endian)
+(define-pmacro (define-alu-insn-un x-basename x-suffix x-op-class x-op-code
+                 x-endian x-mode x-semop)
   (dni (.sym x-basename x-suffix x-endian)
        (.str x-basename x-suffix)
        ((ISA (.sym ebpf x-endian)))
        (.str x-basename x-suffix " $dst" x-endian)
        (+ (f-imm32 0) (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
-          x-op-class OP_SRC_K x-op-code) () ()))
+          x-op-class OP_SRC_K x-op-code)
+       (set x-mode (.sym dst x-endian) (x-semop x-mode (.sym dst x-endian)))
+       ()))
 
-(define-pmacro (define-alu-insn-bin x-basename x-suffix x-op-class x-op-code x-endian)
+(define-pmacro (define-alu-insn-bin x-basename x-suffix x-op-class x-op-code
+                 x-endian x-mode x-semop)
   (begin
+    ;; dst = dst OP immediate
     (dni (.sym x-basename x-suffix "i" x-endian)
          (.str x-basename x-suffix " immediate")
          ((ISA (.sym ebpf x-endian)))
          (.str x-basename x-suffix " $dst" x-endian ",$imm32")
          (+ imm32 (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
-            x-op-class OP_SRC_K x-op-code) () ())
+            x-op-class OP_SRC_K x-op-code)
+         (set x-mode (.sym dst x-endian) (x-semop x-mode (.sym dst x-endian) imm32))
+         ())
+    ;; dst = dst OP src
     (dni (.sym x-basename x-suffix "r" x-endian)
          (.str x-basename x-suffix " register")
          ((ISA (.sym ebpf x-endian)))
          (.str x-basename x-suffix " $dst" x-endian ",$src" x-endian)
          (+ (f-imm32 0) (f-offset16 0) (.sym src x-endian) (.sym dst x-endian)
-            x-op-class OP_SRC_X x-op-code) () ())))
+            x-op-class OP_SRC_X x-op-code)
+         (set x-mode (.sym dst x-endian)
+                      (x-semop x-mode (.sym dst x-endian) (.sym src x-endian)))
+         ())))
+
+(define-pmacro (define-alu-insn-mov x-basename x-suffix x-op-class x-op-code
+                 x-endian x-mode)
+  (begin
+    (dni (.sym mov x-suffix "i" x-endian)
+         (.str mov x-suffix " immediate")
+         ((ISA (.sym ebpf x-endian)))
+         (.str x-basename x-suffix " $dst" x-endian ",$imm32")
+         (+ imm32 (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
+            x-op-class OP_SRC_K x-op-code)
+         (set x-mode (.sym dst x-endian) imm32)
+         ())
+    (dni (.sym mov x-suffix "r" x-endian)
+         (.str mov x-suffix " register")
+         ((ISA (.sym ebpf x-endian)))
+         (.str x-basename x-suffix " $dst" x-endian ",$src" x-endian)
+         (+ (f-imm32 0) (f-offset16 0) (.sym src x-endian) (.sym dst x-endian)
+            x-op-class OP_SRC_X x-op-code)
+         (set x-mode (.sym dst x-endian) (.sym src x-endian))
+         ())))
+
 
-(define-pmacro (daiu x-basename x-op-code x-endian)
+;; Unary ALU instructions (neg)
+(define-pmacro (daiu x-basename x-op-code x-endian x-semop)
   (begin
-    (define-alu-insn-un x-basename "" OP_CLASS_ALU64 x-op-code x-endian)
-    (define-alu-insn-un x-basename "32" OP_CLASS_ALU x-op-code x-endian)))
+    (define-alu-insn-un x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI x-semop)
+    (define-alu-insn-un x-basename "32" OP_CLASS_ALU x-op-code x-endian USI x-semop)))
 
-(define-pmacro (daib x-basename x-op-code x-endian)
+;; Binary ALU instructions (all the others)
+;; For ALU32: DST = (u32) DST OP (u32) SRC is correct semantics
+(define-pmacro (daib x-basename x-op-code x-endian x-semop)
   (begin
-    (define-alu-insn-bin x-basename "" OP_CLASS_ALU64 x-op-code x-endian)
-    (define-alu-insn-bin x-basename "32" OP_CLASS_ALU x-op-code x-endian)))
+    (define-alu-insn-bin x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI x-semop)
+    (define-alu-insn-bin x-basename "32" OP_CLASS_ALU x-op-code x-endian USI x-semop)))
+
+;; Move ALU instructions (mov)
+(define-pmacro (daim x-basename x-op-code x-endian)
+  (begin
+    (define-alu-insn-mov x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI)
+    (define-alu-insn-mov x-basename "32" OP_CLASS_ALU x-op-code x-endian USI)))
 
 (define-pmacro (define-alu-instructions x-endian)
   (begin
-    (daib add OP_CODE_ADD x-endian)
-    (daib sub OP_CODE_SUB x-endian)
-    (daib mul OP_CODE_MUL x-endian)
-    (daib div OP_CODE_DIV x-endian)
-    (daib or  OP_CODE_OR x-endian)
-    (daib and OP_CODE_AND x-endian)
-    (daib lsh OP_CODE_LSH x-endian)
-    (daib rsh OP_CODE_RSH x-endian)
-    (daib mod OP_CODE_MOD x-endian)
-    (daib xor OP_CODE_XOR x-endian)
-    (daib mov OP_CODE_MOV x-endian)
-    (daib arsh OP_CODE_ARSH x-endian)
-    (daiu neg OP_CODE_NEG x-endian)))
+    (daib add OP_CODE_ADD x-endian add)
+    (daib sub OP_CODE_SUB x-endian sub)
+    (daib mul OP_CODE_MUL x-endian mul)
+    (daib div OP_CODE_DIV x-endian div)
+    (daib or  OP_CODE_OR x-endian or)
+    (daib and OP_CODE_AND x-endian and)
+    (daib lsh OP_CODE_LSH x-endian sll)
+    (daib rsh OP_CODE_RSH x-endian srl)
+    (daib mod OP_CODE_MOD x-endian mod)
+    (daib xor OP_CODE_XOR x-endian xor)
+    (daib arsh OP_CODE_ARSH x-endian sra)
+    (daiu neg OP_CODE_NEG x-endian neg)
+    (daim mov OP_CODE_MOV x-endian)))
 
 (define-alu-instructions le)
 (define-alu-instructions be)
@@ -438,7 +490,10 @@
        ((ISA (.sym ebpf x-endian)))
        (.str "end" x-suffix " $dst" x-endian ",$endsize")
        (+  (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian) endsize
-           OP_CLASS_ALU x-op-src OP_CODE_END) () ()))
+           OP_CLASS_ALU x-op-src OP_CODE_END)
+       (set (.sym dst x-endian)
+            (c-call DI "bpfbf_end" (.sym dst x-endian) endsize))
+       ()))
 
 (define-endian-insn "le" OP_SRC_K le)
 (define-endian-insn "be" OP_SRC_X le)
@@ -461,7 +516,9 @@
        (.str "lddw $dst" x-endian ",$imm64")
        (+ imm64 (f-offset16 0) ((.sym f-src x-endian) 0)
           (.sym dst x-endian)
-          OP_CLASS_LD OP_SIZE_DW OP_MODE_IMM) () ()))
+          OP_CLASS_LD OP_SIZE_DW OP_MODE_IMM)
+       (set DI (.sym dst x-endian) imm64)
+       ()))
 
 (define-lddw le)
 (define-lddw be)
@@ -471,19 +528,33 @@
 ;;
 ;; LDABS{w,h,b,dw}
 
-(define-pmacro (dlabs x-suffix x-size)
+(define-pmacro (dlabs x-suffix x-size x-smode)
   (dni (.sym "ldabs" x-suffix)
        (.str "ldabs" x-suffix)
        (all-isas)
        (.str "ldabs" x-suffix " $imm32")
        (+ imm32 (f-offset16 0) (f-regs 0)
           OP_CLASS_LD OP_MODE_ABS (.sym OP_SIZE_ x-size))
-       () ()))
-
-(dlabs "w" W)
-(dlabs "h" H)
-(dlabs "b" B)
-(dlabs "dw" DW)
+       (set x-smode
+            (reg x-smode h-gpr 0)
+            (mem x-smode
+                 (add DI
+                      (mem DI
+                           (add DI
+                                (reg DI h-gpr 6) ;; Pointer to struct sk_buff
+                                (const DI 0)))   ;; XXX offsetof
+                      ;; (struct sk_buff, data) XXX but the offset
+                      ;; depends on CONFIG_* options, so this should
+                      ;; be configured in the simulator and driven by
+                      ;; command-line options.  Handle with a c-call.
+                      imm32)))
+       ;; XXX this clobbers R1-R5
+       ()))
+
+(dlabs "w" W SI)
+(dlabs "h" H HI)
+(dlabs "b" B QI)
+(dlabs "dw" DW DI)
 
 ;; The indirect load instructions are non-generic loads designed to be
 ;; used in socket filters.  They come in several variants:
@@ -491,21 +562,37 @@
 ;; LDIND{w,h,b,dw}le for the little-endian ISA
 ;; LDIND[w,h,b,dw}be for the big-endian ISA
 
-(define-pmacro (dlind x-suffix x-size x-endian)
+(define-pmacro (dlind x-suffix x-size x-endian x-smode)
   (dni (.sym "ldind" x-suffix x-endian)
        (.str "ldind" x-suffix)
        ((ISA (.sym ebpf x-endian)))
        (.str "ldind" x-suffix " $src" x-endian ",$imm32")
        (+ imm32 (f-offset16 0) ((.sym f-dst x-endian) 0) (.sym src x-endian)
           OP_CLASS_LD OP_MODE_IND (.sym OP_SIZE_ x-size))
-       () ()))
+       (set x-smode
+            (reg x-smode h-gpr 0)
+            (mem x-smode
+                 (add DI
+                      (mem DI
+                           (add DI
+                                (reg DI h-gpr 6) ;; Pointer to struct sk_buff
+                                (const DI 0)))   ;; XXX offsetof
+                      ;; (struct sk_buff, data) XXX but the offset
+                      ;; depends on CONFIG_* options, so this should
+                      ;; be configured in the simulator and driven by
+                      ;; command-line options.  Handle with a c-call.
+                      (add DI
+                           (.sym src x-endian)
+                           imm32))))
+       ;; XXX this clobbers R1-R5
+       ()))
 
 (define-pmacro (define-ldind x-endian)
   (begin    
-    (dlind "w" W x-endian)
-    (dlind "h" H x-endian)
-    (dlind "b" B x-endian)
-    (dlind "dw" DW x-endian)))
+    (dlind "w" W x-endian SI)
+    (dlind "h" H x-endian HI)
+    (dlind "b" B x-endian QI)
+    (dlind "dw" DW x-endian DI)))
 
 (define-ldind le)
 (define-ldind be)
@@ -520,35 +607,41 @@
 ;; Loads operate on [$SRC+-OFFSET] -> $DST
 ;; Stores operate on $SRC -> [$DST+-OFFSET]
 
-(define-pmacro (dxli x-basename x-suffix x-size x-endian)
+(define-pmacro (dxli x-basename x-suffix x-size x-endian x-mode)
   (dni (.sym x-basename x-suffix x-endian)
        (.str x-basename x-suffix)
        ((ISA (.sym ebpf x-endian)))
        (.str x-basename x-suffix " $dst" x-endian ",[$src" x-endian "+$offset16]")
        (+ (f-imm32 0) offset16 (.sym src x-endian) (.sym dst x-endian)
           OP_CLASS_LDX (.sym OP_SIZE_ x-size) OP_MODE_MEM)
-       () ()))
+       (set x-mode
+            (.sym dst x-endian)
+            (mem x-mode (add DI (.sym src x-endian) (ext DI (trunc HI offset16)))))
+       ()))
 
-(define-pmacro (dxsi x-basename x-suffix x-size x-endian)
+(define-pmacro (dxsi x-basename x-suffix x-size x-endian x-mode)
   (dni (.sym x-basename x-suffix x-endian)
        (.str x-basename x-suffix)
        ((ISA (.sym ebpf x-endian)))
        (.str x-basename x-suffix " [$dst" x-endian "+$offset16],$src" x-endian)
        (+ (f-imm32 0) offset16 (.sym src x-endian) (.sym dst x-endian)
           OP_CLASS_STX (.sym OP_SIZE_ x-size) OP_MODE_MEM)
-       () ()))
+       (set x-mode
+            (mem x-mode (add DI (.sym dst x-endian) (ext DI (trunc HI offset16))))
+            (.sym src x-endian)) ;; XXX address is section-relative
+       ()))
 
 (define-pmacro (define-ldstx-insns x-endian)
   (begin
-    (dxli "ldx" "w" W x-endian)
-    (dxli "ldx" "h" H x-endian)
-    (dxli "ldx" "b" B x-endian)
-    (dxli "ldx" "dw" DW x-endian)
+    (dxli "ldx" "w" W x-endian SI)
+    (dxli "ldx" "h" H x-endian HI)
+    (dxli "ldx" "b" B x-endian QI)
+    (dxli "ldx" "dw" DW x-endian DI)
 
-    (dxsi "stx" "w" W x-endian)
-    (dxsi "stx" "h" H x-endian)
-    (dxsi "stx" "b" B x-endian)
-    (dxsi "stx" "dw" DW x-endian)))
+    (dxsi "stx" "w" W x-endian SI)
+    (dxsi "stx" "h" H x-endian HI)
+    (dxsi "stx" "b" B x-endian QI)
+    (dxsi "stx" "dw" DW x-endian DI)))
 
 (define-ldstx-insns le)
 (define-ldstx-insns be)
@@ -559,20 +652,24 @@
 ;;  ST{b,h,w,dw}le for the little-endian ISA
 ;;  ST{b,h,w,dw}be for the big-endian ISA
 
-(define-pmacro (dsti x-suffix x-size x-endian)
+(define-pmacro (dsti x-suffix x-size x-endian x-mode)
   (dni (.sym "st" x-suffix x-endian)
        (.str "st" x-suffix)
        ((ISA (.sym ebpf x-endian)))
        (.str "st" x-suffix " [$dst" x-endian "+$offset16],$imm32")
        (+ imm32 offset16 ((.sym f-src x-endian) 0) (.sym dst x-endian)
-          OP_CLASS_ST (.sym OP_SIZE_ x-size) OP_MODE_MEM) () ()))
+          OP_CLASS_ST (.sym OP_SIZE_ x-size) OP_MODE_MEM)
+       (set x-mode
+            (mem x-mode (add DI (.sym dst x-endian) offset16))
+            imm32) ;; XXX address is section-relative
+       ()))
 
 (define-pmacro (define-st-insns x-endian)
   (begin
-    (dsti "b" B x-endian)
-    (dsti "h" H x-endian)
-    (dsti "w" W x-endian)
-    (dsti "dw" DW x-endian)))
+    (dsti "b" B x-endian QI)
+    (dsti "h" H x-endian HI)
+    (dsti "w" W x-endian SI)
+    (dsti "dw" DW x-endian DI)))
 
 (define-st-insns le)
 (define-st-insns be)
@@ -588,64 +685,102 @@
 ;;   J{eq,gt,ge,lt,le,set,ne.sgt,sge,slt,sle}[32]{i,r}be for the
 ;;   big-endian ISA.
 
-(define-pmacro (define-cond-jump-insn x-cond x-suffix x-op-class x-op-code x-endian)
+(define-pmacro (define-cond-jump-insn x-cond x-suffix x-op-class x-op-code x-endian x-mode x-semop)
   (begin
     (dni (.sym j x-cond x-suffix i x-endian)
          (.str j x-cond x-suffix " i")
          ((ISA (.sym ebpf x-endian)))
          (.str "j" x-cond x-suffix " $dst" x-endian ",$imm32,$disp16")
          (+ imm32 disp16 ((.sym f-src x-endian) 0) (.sym dst x-endian)
-            x-op-class OP_SRC_K (.sym OP_CODE_ x-op-code)) () ())
+            x-op-class OP_SRC_K (.sym OP_CODE_ x-op-code))
+         (if VOID (x-semop x-mode (.sym dst x-endian) imm32)
+             (set DI
+                  (reg DI h-pc) (add DI (reg DI h-pc)
+                                     (mul DI (add HI disp16 1) 8))))
+         ())
     (dni (.sym j x-cond x-suffix r x-endian)
          (.str j x-cond x-suffix " r")
          ((ISA (.sym ebpf x-endian)))
          (.str "j" x-cond x-suffix " $dst" x-endian ",$src" x-endian ",$disp16")
          (+ (f-imm32 0) disp16 (.sym src x-endian) (.sym dst x-endian)
-            x-op-class OP_SRC_X (.sym OP_CODE_ x-op-code)) () ())))
-
-(define-pmacro (dcji x-cond x-op-code x-endian)
+            x-op-class OP_SRC_X (.sym OP_CODE_ x-op-code))
+         (if VOID (x-semop x-mode (.sym dst x-endian) (.sym src x-endian))
+             (set DI
+                  (reg DI h-pc) (add DI (reg DI h-pc)
+                                     (mul DI (add HI disp16 1) 8))))
+         ())))
+
+(define-pmacro (dcji x-cond x-op-code x-endian x-semop)
   (begin
-    (define-cond-jump-insn x-cond "" OP_CLASS_JMP x-op-code x-endian)
-    (define-cond-jump-insn x-cond "32" OP_CLASS_JMP32 x-op-code x-endian)))
+    (define-cond-jump-insn x-cond "" OP_CLASS_JMP x-op-code x-endian DI x-semop)
+    (define-cond-jump-insn x-cond "32" OP_CLASS_JMP32 x-op-code x-endian SI x-semop )))
 
 (define-pmacro (define-condjump-insns x-endian)
   (begin
-    (dcji "eq" JEQ x-endian)
-    (dcji "gt" JGT x-endian)
-    (dcji "ge" JGE x-endian)
-    (dcji "lt" JLT x-endian)
-    (dcji "le" JLE x-endian)
-    (dcji "set" JSET x-endian)
-    (dcji "ne" JNE x-endian)
-    (dcji "sgt" JSGT x-endian)
-    (dcji "sge" JSGE x-endian)
-    (dcji "slt" JSLT x-endian)
-    (dcji "sle" JSLE x-endian)))
+    (dcji "eq" JEQ x-endian eq)
+    (dcji "gt" JGT x-endian gtu)
+    (dcji "ge" JGE x-endian geu)
+    (dcji "lt" JLT x-endian ltu)
+    (dcji "le" JLE x-endian leu)
+    (dcji "set" JSET x-endian and)
+    (dcji "ne" JNE x-endian ne)
+    (dcji "sgt" JSGT x-endian gt)
+    (dcji "sge" JSGE x-endian ge)
+    (dcji "slt" JSLT x-endian lt)
+    (dcji "sle" JSLE x-endian le)))
 
 (define-condjump-insns le)
 (define-condjump-insns be)
 
-;; The jump-always, `call' and `exit' instructions dont make use of
-;; either source nor destination registers, so only one variant per
+;; The `call' instruction doesn't make use of registers, but the
+;; semantic routine should have access to the src register in order to
+;; properly interpret the meaning of disp32.  Therefore we need one
+;; version per ISA.
+
+(define-pmacro (define-call-insn x-endian)
+  (dni (.sym call x-endian)
+       "call"
+       ((ISA (.sym ebpf x-endian)))
+       "call $disp32"
+       (+ disp32 (f-offset16 0) (f-regs 0)
+          OP_CLASS_JMP OP_SRC_K OP_CODE_CALL)
+       (c-call VOID
+               "bpfbf_call" disp32 (ifield (.sym f-src x-endian)))
+       ()))
+
+(define-call-insn le)
+(define-call-insn be)
+
+;; The jump-always and `exit' instructions dont make use of either
+;; source nor destination registers, so only one variant per
 ;; instruction is defined.
 
 (dni ja "ja" (all-isas) "ja $disp16"
      (+ (f-imm32 0) disp16 (f-regs 0)
-        OP_CLASS_JMP OP_SRC_K OP_CODE_JA) () ())
-
-(dni call "call" (all-isas) "call $disp32"
-     (+ disp32 (f-offset16 0) (f-regs 0)
-        OP_CLASS_JMP OP_SRC_K OP_CODE_CALL) () ())
+        OP_CLASS_JMP OP_SRC_K OP_CODE_JA)
+     (set DI (reg DI h-pc) (add DI (reg DI h-pc)
+                                (mul DI (add HI disp16 1) 8)))
+     ())
 
 (dni "exit" "exit" (all-isas) "exit"
      (+ (f-imm32 0) (f-offset16 0) (f-regs 0)
-        OP_CLASS_JMP (f-op-src 0) OP_CODE_EXIT) () ())
+        OP_CLASS_JMP (f-op-src 0) OP_CODE_EXIT)
+     (c-call VOID "bpfbf_exit")
+     ())
 
 ;;; Atomic instructions
 
 ;; The atomic exchange-and-add instructions come in two flavors: one
 ;; for swapping 64-bit quantities and another for 32-bit quantities.
 
+(define-pmacro (sem-exchange-and-add x-endian x-mode)
+  (sequence VOID ((x-mode tmp))
+            ;; XXX acquire lock in simulator...  as a hardware element?
+            (set x-mode tmp (mem x-mode (add DI (.sym dst x-endian) offset16)))
+            (set x-mode
+                 (mem x-mode (add DI (.sym dst x-endian) offset16))
+                 (add x-mode tmp (.sym src x-endian)))))
+
 (define-pmacro (define-atomic-insns x-endian)
   (begin
     (dni (.str "xadddw" x-endian)
@@ -653,13 +788,28 @@
          ((ISA (.sym ebpf x-endian)))
          (.str "xadddw [$dst" x-endian "+$offset16],$src" x-endian)
          (+ (f-imm32 0) (.sym src x-endian) (.sym dst x-endian)
-            offset16 OP_MODE_XADD OP_SIZE_DW OP_CLASS_STX) () ())
+            offset16 OP_MODE_XADD OP_SIZE_DW OP_CLASS_STX)
+         (sem-exchange-and-add x-endian DI)
+         ())
     (dni (.str "xaddw" x-endian)
          "xaddw"
          ((ISA (.sym ebpf x-endian)))
          (.str "xaddw [$dst" x-endian "+$offset16],$src" x-endian)
          (+ (f-imm32 0) (.sym src x-endian) (.sym dst x-endian)
-            offset16 OP_MODE_XADD OP_SIZE_W OP_CLASS_STX) () ())))
+            offset16 OP_MODE_XADD OP_SIZE_W OP_CLASS_STX)
+         (sem-exchange-and-add x-endian SI)
+         ())))
 
 (define-atomic-insns le)
 (define-atomic-insns be)
+
+;;; Breakpoint instruction
+
+;; The brkpt instruction is used by the BPF simulator and it doesn't
+;; really belong to the eBPF instruction set.
+
+(dni "brkpt" "brkpt" (all-isas)  "brkpt"
+     (+ (f-imm32 0) (f-offset16 0) (f-regs 0)
+        OP_CLASS_ALU OP_SRC_X OP_CODE_NEG)
+     (c-call VOID "bpfbf_breakpoint")
+     ())
diff --git a/cpu/bpf.opc b/cpu/bpf.opc
index e70ee04..e2acaa4 100644
--- a/cpu/bpf.opc
+++ b/cpu/bpf.opc
@@ -129,6 +129,7 @@ bpf_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 
   info->bytes_per_chunk = 1;
   info->bytes_per_line = 8;
+  info->endian_code = BFD_ENDIAN_BIG;
 
   /* Attempt to read the base part of the insn.  */
   buflen = cd->base_insn_bitsize / 8;