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author | DJ Delorie <dj@redhat.com> | 2005-12-14 03:30:07 +0000 |
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committer | DJ Delorie <dj@redhat.com> | 2005-12-14 03:30:07 +0000 |
commit | eda87aba05086a3cef1cafe3ca76c2139727a47e (patch) | |
tree | 9d03636a44f1dcb9f1de737d50a0840fe94675b7 /cpu | |
parent | bbc434cbc9a182f13eb4cacd9fae9c4b344fc7c2 (diff) | |
download | gdb-eda87aba05086a3cef1cafe3ca76c2139727a47e.zip gdb-eda87aba05086a3cef1cafe3ca76c2139727a47e.tar.gz gdb-eda87aba05086a3cef1cafe3ca76c2139727a47e.tar.bz2 |
* m32c.cpu (jsri): Fix order so register names aren't treated as
symbols.
(indexb, indexbd, indexbs, indexl, indexld, indexls, indexw,
indexwd, indexws): Fix encodings.
* m32c-desc.c: Regenerate.
* m32c-opc.c: Regenerate.
* m32c-opc.h: Regenerate.
Diffstat (limited to 'cpu')
-rw-r--r-- | cpu/ChangeLog | 7 | ||||
-rw-r--r-- | cpu/m32c.cpu | 30 |
2 files changed, 24 insertions, 13 deletions
diff --git a/cpu/ChangeLog b/cpu/ChangeLog index f2d1d7d..86bd136 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,3 +1,10 @@ +2005-12-13 DJ Delorie <dj@redhat.com> + + * m32c.cpu (jsri): Fix order so register names aren't treated as + symbols. + (indexb, indexbd, indexbs, indexl, indexld, indexls, indexw, + indexwd, indexws): Fix encodings. + 2005-12-12 Nathan Sidwell <nathan@codesourcery.com> * mt.cpu: Rename from ms1.cpu. diff --git a/cpu/m32c.cpu b/cpu/m32c.cpu index cb892ff..a16c0c2 100644 --- a/cpu/m32c.cpu +++ b/cpu/m32c.cpu @@ -7979,33 +7979,36 @@ (define-pmacro (indexls-sem mode d) (set SrcIndex (sll d (const 2))) (set DstIndex (const 0))) +; Note that "wbit" not where the size bit goes here, hence, it's +; always 0 in these calls but op2 differs instead. + ; indexb src (index byte) (unary32-defn QI .b 0 indexb #x8 0 #x3 indexb-sem) -(unary32-defn HI .w 1 indexb #x8 1 #x3 indexb-sem) +(unary32-defn HI .w 0 indexb #x8 1 #x3 indexb-sem) ; indexbd src (index byte dest) (unary32-defn QI .b 0 indexbd #xA 0 3 indexbd-sem) -(unary32-defn HI .w 1 indexbd #xA 1 3 indexbd-sem) +(unary32-defn HI .w 0 indexbd #xA 1 3 indexbd-sem) ; indexbs src (index byte src) (unary32-defn QI .b 0 indexbs #xC 0 3 indexbs-sem) -(unary32-defn HI .w 1 indexbs #xC 1 3 indexbs-sem) +(unary32-defn HI .w 0 indexbs #xC 1 3 indexbs-sem) ; indexl src (index long) (unary32-defn QI .b 0 indexl 9 2 3 indexl-sem) -(unary32-defn HI .w 1 indexl 9 3 3 indexl-sem) +(unary32-defn HI .w 0 indexl 9 3 3 indexl-sem) ; indexld src (index long dest) (unary32-defn QI .b 0 indexld #xB 2 3 indexld-sem) -(unary32-defn HI .w 1 indexld #xB 3 3 indexld-sem) +(unary32-defn HI .w 0 indexld #xB 3 3 indexld-sem) ; indexls src (index long src) (unary32-defn QI .b 0 indexls 9 0 3 indexls-sem) -(unary32-defn HI .w 1 indexls 9 1 3 indexls-sem) +(unary32-defn HI .w 0 indexls 9 1 3 indexls-sem) ; indexw src (index word) (unary32-defn QI .b 0 indexw 8 2 3 indexw-sem) -(unary32-defn HI .w 1 indexw 8 3 3 indexw-sem) +(unary32-defn HI .w 0 indexw 8 3 3 indexw-sem) ; indexwd src (index word dest) (unary32-defn QI .b 0 indexwd #xA 2 3 indexwd-sem) -(unary32-defn HI .w 1 indexwd #xA 3 3 indexwd-sem) +(unary32-defn HI .w 0 indexwd #xA 3 3 indexwd-sem) ; indexws (index word src) (unary32-defn QI .b 0 indexws #xC 2 3 indexws-sem) -(unary32-defn HI .w 1 indexws #xC 3 3 indexws-sem) +(unary32-defn HI .w 0 indexws #xC 3 3 indexws-sem) ;------------------------------------------------------------- ; jcc - jump on condition @@ -8218,12 +8221,12 @@ ) ) ; jsri.w dst (m16 #1 m32 #1)) -(jsri-defn w dst16-basic-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem - dst32-basic-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 2) (jsri-defn w dst16-16-8-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem dst32-16-8-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 3) (jsri-defn w dst16-16-16-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem dst32-16-16-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 4) +(jsri-defn w dst16-basic-HI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x3) jsr16-sem + dst32-basic-Unprefixed-HI (f-0-4 #xC) (f-7-1 1) (f-10-2 #x1) (f-12-4 #xF) jsr32-sem 2) (dni jsri32.w "jsr.w dst32-16-24-Unprefixed-HI" ((machine 32)) ("jsri.w ${dst32-16-24-Unprefixed-HI}") (+ (f-0-4 #xC) (f-7-1 1) dst32-16-24-Unprefixed-HI (f-10-2 #x1) (f-12-4 #xF)) @@ -8231,12 +8234,13 @@ ()) ; jsri.a (m16 #2 m32 #2) -(jsri-defn a dst16-basic-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem - dst32-basic-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 2) (jsri-defn a dst16-16-8-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem dst32-16-8-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 3) (jsri-defn a dst16-16-16-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem dst32-16-16-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 4) +(jsri-defn a dst16-basic-SI (f-0-4 #x7) (f-4-4 #xD) (f-8-4 #x1) jsr16-sem + dst32-basic-Unprefixed-SI (f-0-4 #x9) (f-7-1 0) (f-10-2 #x0) (f-12-4 #x1) jsr32-sem 2) + (dni jsri32.a "jsr.w dst32-16-24-Unprefixed-HI" ((machine 32)) ("jsri.w ${dst32-16-24-Unprefixed-SI}") (+ (f-0-4 #x9) (f-7-1 0) dst32-16-24-Unprefixed-SI (f-10-2 #x0) (f-12-4 #x1)) |