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| author | nobody <> | 2005-11-01 22:57:24 +0000 |
|---|---|---|
| committer | nobody <> | 2005-11-01 22:57:24 +0000 |
| commit | e97bf4462428241425b287215aa9fd48478b3c36 (patch) | |
| tree | fc92693b860773c8fdb9bd836cae7434dc790216 /cpu | |
| parent | 25cf6930c89092db8bd48cf98b88dd2e258f93f6 (diff) | |
| download | gdb-e97bf4462428241425b287215aa9fd48478b3c36.zip gdb-e97bf4462428241425b287215aa9fd48478b3c36.tar.gz gdb-e97bf4462428241425b287215aa9fd48478b3c36.tar.bz2 | |
This commit was manufactured by cvs2svn to create branch 'gdb_6_4-branch'.gdb_6_4-2005-11-01-branchpoint
Sprout from gdb-csl-arm-20051020-branch 2005-10-20 00:09:02 UTC nobody 'This commit was manufactured by cvs2svn to create branch 'gdb-csl-'
Cherrypick from master 2005-11-01 22:57:23 UTC Alan Modra <amodra@gmail.com> ' PR ld/1775':
ChangeLog
Makefile.def
Makefile.in
Makefile.tpl
bfd/ChangeLog
bfd/Makefile.am
bfd/Makefile.in
bfd/aoutx.h
bfd/archures.c
bfd/bfd-in2.h
bfd/bfdwin.c
bfd/cache.c
bfd/coff-rs6000.c
bfd/coff-z80.c
bfd/coff64-rs6000.c
bfd/coffcode.h
bfd/config.bfd
bfd/configure
bfd/configure.in
bfd/cpu-ia64-opc.c
bfd/cpu-z80.c
bfd/dep-in.sed
bfd/elf-bfd.h
bfd/elf.c
bfd/elf32-arm.c
bfd/elf32-bfin.c
bfd/elf32-cris.c
bfd/elf32-hppa.c
bfd/elf32-i370.c
bfd/elf32-i386.c
bfd/elf32-m32r.c
bfd/elf32-m68k.c
bfd/elf32-ppc.c
bfd/elf32-s390.c
bfd/elf32-sh.c
bfd/elf64-ppc.c
bfd/elf64-s390.c
bfd/elf64-x86-64.c
bfd/elflink.c
bfd/elfxx-ia64.c
bfd/elfxx-mips.c
bfd/elfxx-mips.h
bfd/elfxx-sparc.c
bfd/elfxx-sparc.h
bfd/hppabsd-core.c
bfd/hpux-core.c
bfd/libbfd-in.h
bfd/libbfd.c
bfd/libbfd.h
bfd/linker.c
bfd/osf-core.c
bfd/po/SRC-POTFILES.in
bfd/po/bfd.pot
bfd/reloc.c
bfd/rs6000-core.c
bfd/sco5-core.c
bfd/targets.c
bfd/trad-core.c
bfd/version.h
bfd/xcoff-target.h
cpu/ChangeLog
cpu/frv.opc
cpu/m32c.cpu
cpu/m32c.opc
cpu/m32r.opc
depcomp
etc/ChangeLog
etc/texi2pod.pl
gdb/ChangeLog
gdb/Makefile.in
gdb/NEWS
gdb/config/i386/tm-cygwin.h
gdb/config/iq2000/iq2000.mt
gdb/config/ms1/ms1.mt
gdb/doc/ChangeLog
gdb/doc/gdb.texinfo
gdb/doublest.c
gdb/dwarf2read.c
gdb/event-top.c
gdb/gdbserver/ChangeLog
gdb/gdbserver/linux-ia64-low.c
gdb/gdbserver/server.c
gdb/hppa-hpux-tdep.c
gdb/hppa-tdep.h
gdb/inf-ttrace.c
gdb/main.c
gdb/mi/gdb-mi.el
gdb/po/gdbtext
gdb/ppc-tdep.h
gdb/regformats/reg-ia64.dat
gdb/rs6000-tdep.c
gdb/testsuite/ChangeLog
gdb/testsuite/gdb.ada/array_return/p.adb
gdb/testsuite/gdb.ada/array_return/pck.adb
gdb/testsuite/gdb.ada/array_return/pck.ads
gdb/testsuite/gdb.ada/arrayidx/p.adb
gdb/testsuite/gdb.asm/asm-source.exp
gdb/testsuite/gdb.base/bfp-test.exp
gdb/tui/tui-command.c
gdb/tui/tui-data.c
gdb/tui/tui-data.h
gdb/tui/tui-disasm.c
gdb/tui/tui-layout.c
gdb/tui/tui-source.c
gdb/tui/tui-source.h
gdb/tui/tui-stack.c
gdb/tui/tui-win.c
gdb/tui/tui-winsource.c
gdb/tui/tui-winsource.h
gdb/vax-tdep.c
gdb/version.in
gdb/win32-nat.c
include/ChangeLog
include/coff/ChangeLog
include/coff/internal.h
include/coff/z80.h
include/dis-asm.h
include/elf/ChangeLog
include/floatformat.h
include/opcode/ChangeLog
include/opcode/cgen-bitset.h
include/opcode/cgen.h
include/opcode/ia64.h
libiberty/ChangeLog
libiberty/floatformat.c
opcodes/ChangeLog
opcodes/Makefile.am
opcodes/Makefile.in
opcodes/arm-dis.c
opcodes/bfin-dis.c
opcodes/cgen-dis.in
opcodes/cgen-opc.c
opcodes/configure
opcodes/configure.in
opcodes/dep-in.sed
opcodes/disassemble.c
opcodes/fr30-desc.c
opcodes/fr30-desc.h
opcodes/fr30-dis.c
opcodes/fr30-opc.c
opcodes/frv-desc.c
opcodes/frv-desc.h
opcodes/frv-dis.c
opcodes/frv-opc.c
opcodes/frv-opc.h
opcodes/ia64-asmtab.c
opcodes/ip2k-desc.c
opcodes/ip2k-desc.h
opcodes/ip2k-dis.c
opcodes/ip2k-opc.c
opcodes/m32c-asm.c
opcodes/m32c-desc.c
opcodes/m32c-desc.h
opcodes/m32c-dis.c
opcodes/m32c-ibld.c
opcodes/m32c-opc.c
opcodes/m32c-opc.h
opcodes/m32r-asm.c
opcodes/m32r-desc.c
opcodes/m32r-desc.h
opcodes/m32r-dis.c
opcodes/m32r-opc.c
opcodes/ms1-desc.c
opcodes/ms1-desc.h
opcodes/ms1-dis.c
opcodes/openrisc-desc.c
opcodes/openrisc-desc.h
opcodes/openrisc-dis.c
opcodes/openrisc-opc.c
opcodes/po/POTFILES.in
opcodes/po/opcodes.pot
opcodes/xstormy16-desc.c
opcodes/xstormy16-desc.h
opcodes/xstormy16-dis.c
opcodes/xstormy16-opc.c
opcodes/z80-dis.c
sim/frv/ChangeLog
sim/frv/arch.c
sim/frv/arch.h
sim/frv/cpu.c
sim/frv/cpu.h
sim/frv/cpuall.h
sim/frv/decode.c
sim/frv/decode.h
sim/frv/frv-sim.h
sim/frv/mloop.in
sim/frv/model.c
sim/frv/pipeline.c
sim/frv/sem.c
sim/frv/traps.c
Delete:
intl/ChangeLog
intl/Makefile.in
intl/acconfig.h
intl/aclocal.m4
intl/bindtextdom.c
intl/cat-compat.c
intl/config.in
intl/configure
intl/configure.in
intl/dcgettext.c
intl/dgettext.c
intl/explodename.c
intl/finddomain.c
intl/gettext.c
intl/gettext.h
intl/gettextP.h
intl/hash-string.h
intl/intl-compat.c
intl/intlh.inst.in
intl/l10nflist.c
intl/libgettext.h
intl/libintl.glibc
intl/linux-msg.sed
intl/loadinfo.h
intl/loadmsgcat.c
intl/localealias.c
intl/po2tbl.sed.in
intl/textdomain.c
intl/xopen-msg.sed
mmalloc/COPYING.LIB
mmalloc/ChangeLog
mmalloc/MAINTAINERS
mmalloc/Makefile.in
mmalloc/TODO
mmalloc/acinclude.m4
mmalloc/aclocal.m4
mmalloc/attach.c
mmalloc/configure
mmalloc/configure.in
mmalloc/detach.c
mmalloc/keys.c
mmalloc/mcalloc.c
mmalloc/mfree.c
mmalloc/mm.c
mmalloc/mmalloc.c
mmalloc/mmalloc.h
mmalloc/mmalloc.texi
mmalloc/mmap-sup.c
mmalloc/mmcheck.c
mmalloc/mmemalign.c
mmalloc/mmprivate.h
mmalloc/mmstats.c
mmalloc/mmtrace.awk
mmalloc/mmtrace.c
mmalloc/mrealloc.c
mmalloc/mvalloc.c
mmalloc/sbrk-sup.c
sim/sh64/ChangeLog
sim/sh64/Makefile.in
sim/sh64/arch.c
sim/sh64/arch.h
sim/sh64/config.in
sim/sh64/configure
sim/sh64/configure.ac
sim/sh64/cpu.c
sim/sh64/cpu.h
sim/sh64/cpuall.h
sim/sh64/decode-compact.c
sim/sh64/decode-compact.h
sim/sh64/decode-media.c
sim/sh64/decode-media.h
sim/sh64/decode.h
sim/sh64/defs-compact.h
sim/sh64/defs-media.h
sim/sh64/eng-compact.h
sim/sh64/eng-media.h
sim/sh64/eng.h
sim/sh64/mloop-compact.c
sim/sh64/mloop-media.c
sim/sh64/sem-compact-switch.c
sim/sh64/sem-compact.c
sim/sh64/sem-media-switch.c
sim/sh64/sem-media.c
sim/sh64/sh-desc.c
sim/sh64/sh-desc.h
sim/sh64/sh-opc.h
sim/sh64/sh64-sim.h
sim/sh64/sh64.c
sim/sh64/sim-if.c
sim/sh64/sim-main.h
sim/sh64/tconfig.in
sim/testsuite/sim/sh64/ChangeLog
sim/testsuite/sim/sh64/compact.exp
sim/testsuite/sim/sh64/compact/ChangeLog
sim/testsuite/sim/sh64/compact/add.cgs
sim/testsuite/sim/sh64/compact/addc.cgs
sim/testsuite/sim/sh64/compact/addi.cgs
sim/testsuite/sim/sh64/compact/addv.cgs
sim/testsuite/sim/sh64/compact/and.cgs
sim/testsuite/sim/sh64/compact/andb.cgs
sim/testsuite/sim/sh64/compact/andi.cgs
sim/testsuite/sim/sh64/compact/bf.cgs
sim/testsuite/sim/sh64/compact/bfs.cgs
sim/testsuite/sim/sh64/compact/bra.cgs
sim/testsuite/sim/sh64/compact/braf.cgs
sim/testsuite/sim/sh64/compact/brk.cgs
sim/testsuite/sim/sh64/compact/bsr.cgs
sim/testsuite/sim/sh64/compact/bsrf.cgs
sim/testsuite/sim/sh64/compact/bt.cgs
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sim/testsuite/sim/sh64/compact/clrmac.cgs
sim/testsuite/sim/sh64/compact/clrs.cgs
sim/testsuite/sim/sh64/compact/clrt.cgs
sim/testsuite/sim/sh64/compact/cmpeq.cgs
sim/testsuite/sim/sh64/compact/cmpeqi.cgs
sim/testsuite/sim/sh64/compact/cmpge.cgs
sim/testsuite/sim/sh64/compact/cmpgt.cgs
sim/testsuite/sim/sh64/compact/cmphi.cgs
sim/testsuite/sim/sh64/compact/cmphs.cgs
sim/testsuite/sim/sh64/compact/cmppl.cgs
sim/testsuite/sim/sh64/compact/cmppz.cgs
sim/testsuite/sim/sh64/compact/cmpstr.cgs
sim/testsuite/sim/sh64/compact/div0s.cgs
sim/testsuite/sim/sh64/compact/div0u.cgs
sim/testsuite/sim/sh64/compact/div1.cgs
sim/testsuite/sim/sh64/compact/dmulsl.cgs
sim/testsuite/sim/sh64/compact/dmulul.cgs
sim/testsuite/sim/sh64/compact/dt.cgs
sim/testsuite/sim/sh64/compact/extsb.cgs
sim/testsuite/sim/sh64/compact/extsw.cgs
sim/testsuite/sim/sh64/compact/extub.cgs
sim/testsuite/sim/sh64/compact/extuw.cgs
sim/testsuite/sim/sh64/compact/fabs.cgs
sim/testsuite/sim/sh64/compact/fadd.cgs
sim/testsuite/sim/sh64/compact/fcmpeq.cgs
sim/testsuite/sim/sh64/compact/fcmpgt.cgs
sim/testsuite/sim/sh64/compact/fcnvds.cgs
sim/testsuite/sim/sh64/compact/fcnvsd.cgs
sim/testsuite/sim/sh64/compact/fdiv.cgs
sim/testsuite/sim/sh64/compact/fipr.cgs
sim/testsuite/sim/sh64/compact/fldi0.cgs
sim/testsuite/sim/sh64/compact/fldi1.cgs
sim/testsuite/sim/sh64/compact/flds.cgs
sim/testsuite/sim/sh64/compact/float.cgs
sim/testsuite/sim/sh64/compact/fmac.cgs
sim/testsuite/sim/sh64/compact/fmov.cgs
sim/testsuite/sim/sh64/compact/fmul.cgs
sim/testsuite/sim/sh64/compact/fneg.cgs
sim/testsuite/sim/sh64/compact/frchg.cgs
sim/testsuite/sim/sh64/compact/fschg.cgs
sim/testsuite/sim/sh64/compact/fsqrt.cgs
sim/testsuite/sim/sh64/compact/fsts.cgs
sim/testsuite/sim/sh64/compact/fsub.cgs
sim/testsuite/sim/sh64/compact/ftrc.cgs
sim/testsuite/sim/sh64/compact/ftrv.cgs
sim/testsuite/sim/sh64/compact/jmp.cgs
sim/testsuite/sim/sh64/compact/jsr.cgs
sim/testsuite/sim/sh64/compact/ldc-gbr.cgs
sim/testsuite/sim/sh64/compact/ldcl-gbr.cgs
sim/testsuite/sim/sh64/compact/lds-fpscr.cgs
sim/testsuite/sim/sh64/compact/lds-fpul.cgs
sim/testsuite/sim/sh64/compact/lds-mach.cgs
sim/testsuite/sim/sh64/compact/lds-macl.cgs
sim/testsuite/sim/sh64/compact/lds-pr.cgs
sim/testsuite/sim/sh64/compact/ldsl-fpscr.cgs
sim/testsuite/sim/sh64/compact/ldsl-fpul.cgs
sim/testsuite/sim/sh64/compact/ldsl-mach.cgs
sim/testsuite/sim/sh64/compact/ldsl-macl.cgs
sim/testsuite/sim/sh64/compact/ldsl-pr.cgs
sim/testsuite/sim/sh64/compact/macl.cgs
sim/testsuite/sim/sh64/compact/macw.cgs
sim/testsuite/sim/sh64/compact/mov.cgs
sim/testsuite/sim/sh64/compact/mova.cgs
sim/testsuite/sim/sh64/compact/movb1.cgs
sim/testsuite/sim/sh64/compact/movb10.cgs
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sim/testsuite/sim/sh64/compact/movb3.cgs
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sim/testsuite/sim/sh64/compact/movb9.cgs
sim/testsuite/sim/sh64/compact/movcal.cgs
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sim/testsuite/sim/sh64/compact/movl1.cgs
sim/testsuite/sim/sh64/compact/movl10.cgs
sim/testsuite/sim/sh64/compact/movl11.cgs
sim/testsuite/sim/sh64/compact/movl2.cgs
sim/testsuite/sim/sh64/compact/movl3.cgs
sim/testsuite/sim/sh64/compact/movl4.cgs
sim/testsuite/sim/sh64/compact/movl5.cgs
sim/testsuite/sim/sh64/compact/movl6.cgs
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sim/testsuite/sim/sh64/compact/movl8.cgs
sim/testsuite/sim/sh64/compact/movl9.cgs
sim/testsuite/sim/sh64/compact/movt.cgs
sim/testsuite/sim/sh64/compact/movw1.cgs
sim/testsuite/sim/sh64/compact/movw10.cgs
sim/testsuite/sim/sh64/compact/movw11.cgs
sim/testsuite/sim/sh64/compact/movw2.cgs
sim/testsuite/sim/sh64/compact/movw3.cgs
sim/testsuite/sim/sh64/compact/movw4.cgs
sim/testsuite/sim/sh64/compact/movw5.cgs
sim/testsuite/sim/sh64/compact/movw6.cgs
sim/testsuite/sim/sh64/compact/movw7.cgs
sim/testsuite/sim/sh64/compact/movw8.cgs
sim/testsuite/sim/sh64/compact/movw9.cgs
sim/testsuite/sim/sh64/compact/mull.cgs
sim/testsuite/sim/sh64/compact/mulsw.cgs
sim/testsuite/sim/sh64/compact/muluw.cgs
sim/testsuite/sim/sh64/compact/neg.cgs
sim/testsuite/sim/sh64/compact/negc.cgs
sim/testsuite/sim/sh64/compact/nop.cgs
sim/testsuite/sim/sh64/compact/not.cgs
sim/testsuite/sim/sh64/compact/ocbi.cgs
sim/testsuite/sim/sh64/compact/ocbp.cgs
sim/testsuite/sim/sh64/compact/ocbwb.cgs
sim/testsuite/sim/sh64/compact/or.cgs
sim/testsuite/sim/sh64/compact/orb.cgs
sim/testsuite/sim/sh64/compact/ori.cgs
sim/testsuite/sim/sh64/compact/pref.cgs
sim/testsuite/sim/sh64/compact/rotcl.cgs
sim/testsuite/sim/sh64/compact/rotcr.cgs
sim/testsuite/sim/sh64/compact/rotl.cgs
sim/testsuite/sim/sh64/compact/rotr.cgs
sim/testsuite/sim/sh64/compact/rts.cgs
sim/testsuite/sim/sh64/compact/sets.cgs
sim/testsuite/sim/sh64/compact/sett.cgs
sim/testsuite/sim/sh64/compact/shad.cgs
sim/testsuite/sim/sh64/compact/shal.cgs
sim/testsuite/sim/sh64/compact/shar.cgs
sim/testsuite/sim/sh64/compact/shld.cgs
sim/testsuite/sim/sh64/compact/shll.cgs
sim/testsuite/sim/sh64/compact/shll16.cgs
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sim/testsuite/sim/sh64/compact/shll8.cgs
sim/testsuite/sim/sh64/compact/shlr.cgs
sim/testsuite/sim/sh64/compact/shlr16.cgs
sim/testsuite/sim/sh64/compact/shlr2.cgs
sim/testsuite/sim/sh64/compact/shlr8.cgs
sim/testsuite/sim/sh64/compact/stc-gbr.cgs
sim/testsuite/sim/sh64/compact/stcl-gbr.cgs
sim/testsuite/sim/sh64/compact/sts-fpscr.cgs
sim/testsuite/sim/sh64/compact/sts-fpul.cgs
sim/testsuite/sim/sh64/compact/sts-mach.cgs
sim/testsuite/sim/sh64/compact/sts-macl.cgs
sim/testsuite/sim/sh64/compact/sts-pr.cgs
sim/testsuite/sim/sh64/compact/stsl-fpscr.cgs
sim/testsuite/sim/sh64/compact/stsl-fpul.cgs
sim/testsuite/sim/sh64/compact/stsl-mach.cgs
sim/testsuite/sim/sh64/compact/stsl-macl.cgs
sim/testsuite/sim/sh64/compact/stsl-pr.cgs
sim/testsuite/sim/sh64/compact/sub.cgs
sim/testsuite/sim/sh64/compact/subc.cgs
sim/testsuite/sim/sh64/compact/subv.cgs
sim/testsuite/sim/sh64/compact/swapb.cgs
sim/testsuite/sim/sh64/compact/swapw.cgs
sim/testsuite/sim/sh64/compact/tasb.cgs
sim/testsuite/sim/sh64/compact/testutils.inc
sim/testsuite/sim/sh64/compact/trapa.cgs
sim/testsuite/sim/sh64/compact/tst.cgs
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sim/testsuite/sim/sh64/compact/xtrct.cgs
sim/testsuite/sim/sh64/interwork.exp
sim/testsuite/sim/sh64/media.exp
sim/testsuite/sim/sh64/media/ChangeLog
sim/testsuite/sim/sh64/media/add.cgs
sim/testsuite/sim/sh64/media/addi.cgs
sim/testsuite/sim/sh64/media/addil.cgs
sim/testsuite/sim/sh64/media/addl.cgs
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sim/testsuite/sim/sh64/media/andi.cgs
sim/testsuite/sim/sh64/media/beq.cgs
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sim/testsuite/sim/sh64/media/bge.cgs
sim/testsuite/sim/sh64/media/bgeu.cgs
sim/testsuite/sim/sh64/media/bgt.cgs
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sim/testsuite/sim/sh64/media/blink.cgs
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sim/testsuite/sim/sh64/media/fdivd.cgs
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sim/testsuite/sim/sh64/media/fgetscr.cgs
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sim/testsuite/sim/sh64/media/floatld.cgs
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sim/testsuite/sim/sh64/media/floatqd.cgs
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sim/testsuite/sim/sh64/media/fmacs.cgs
sim/testsuite/sim/sh64/media/fmovd.cgs
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sim/testsuite/sim/sh64/media/fmuld.cgs
sim/testsuite/sim/sh64/media/fmuls.cgs
sim/testsuite/sim/sh64/media/fnegd.cgs
sim/testsuite/sim/sh64/media/fnegs.cgs
sim/testsuite/sim/sh64/media/fputscr.cgs
sim/testsuite/sim/sh64/media/fsqrtd.cgs
sim/testsuite/sim/sh64/media/fsqrts.cgs
sim/testsuite/sim/sh64/media/fstd.cgs
sim/testsuite/sim/sh64/media/fstp.cgs
sim/testsuite/sim/sh64/media/fsts.cgs
sim/testsuite/sim/sh64/media/fstxd.cgs
sim/testsuite/sim/sh64/media/fstxp.cgs
sim/testsuite/sim/sh64/media/fstxs.cgs
sim/testsuite/sim/sh64/media/fsubd.cgs
sim/testsuite/sim/sh64/media/fsubs.cgs
sim/testsuite/sim/sh64/media/ftrcdl.cgs
sim/testsuite/sim/sh64/media/ftrcdq.cgs
sim/testsuite/sim/sh64/media/ftrcsl.cgs
sim/testsuite/sim/sh64/media/ftrcsq.cgs
sim/testsuite/sim/sh64/media/ftrvs.cgs
sim/testsuite/sim/sh64/media/getcfg.cgs
sim/testsuite/sim/sh64/media/getcon.cgs
sim/testsuite/sim/sh64/media/gettr.cgs
sim/testsuite/sim/sh64/media/icbi.cgs
sim/testsuite/sim/sh64/media/ldb.cgs
sim/testsuite/sim/sh64/media/ldhil.cgs
sim/testsuite/sim/sh64/media/ldhiq.cgs
sim/testsuite/sim/sh64/media/ldl.cgs
sim/testsuite/sim/sh64/media/ldlol.cgs
sim/testsuite/sim/sh64/media/ldloq.cgs
sim/testsuite/sim/sh64/media/ldq.cgs
sim/testsuite/sim/sh64/media/ldub.cgs
sim/testsuite/sim/sh64/media/lduw.cgs
sim/testsuite/sim/sh64/media/ldw.cgs
sim/testsuite/sim/sh64/media/ldxb.cgs
sim/testsuite/sim/sh64/media/ldxl.cgs
sim/testsuite/sim/sh64/media/ldxq.cgs
sim/testsuite/sim/sh64/media/ldxub.cgs
sim/testsuite/sim/sh64/media/ldxuw.cgs
sim/testsuite/sim/sh64/media/ldxw.cgs
sim/testsuite/sim/sh64/media/mabsl.cgs
sim/testsuite/sim/sh64/media/mabsw.cgs
sim/testsuite/sim/sh64/media/maddl.cgs
sim/testsuite/sim/sh64/media/maddsl.cgs
sim/testsuite/sim/sh64/media/maddsub.cgs
sim/testsuite/sim/sh64/media/maddsw.cgs
sim/testsuite/sim/sh64/media/maddw.cgs
sim/testsuite/sim/sh64/media/mcmpeqb.cgs
sim/testsuite/sim/sh64/media/mcmpeql.cgs
sim/testsuite/sim/sh64/media/mcmpeqw.cgs
sim/testsuite/sim/sh64/media/mcmpgtl.cgs
sim/testsuite/sim/sh64/media/mcmpgtub.cgs
sim/testsuite/sim/sh64/media/mcmpgtw.cgs
sim/testsuite/sim/sh64/media/mcmv.cgs
sim/testsuite/sim/sh64/media/mcnvslw.cgs
sim/testsuite/sim/sh64/media/mcnvswb.cgs
sim/testsuite/sim/sh64/media/mcnvswub.cgs
sim/testsuite/sim/sh64/media/mextr1.cgs
sim/testsuite/sim/sh64/media/mextr2.cgs
sim/testsuite/sim/sh64/media/mextr3.cgs
sim/testsuite/sim/sh64/media/mextr4.cgs
sim/testsuite/sim/sh64/media/mextr5.cgs
sim/testsuite/sim/sh64/media/mextr6.cgs
sim/testsuite/sim/sh64/media/mextr7.cgs
sim/testsuite/sim/sh64/media/mmacfxwl.cgs
sim/testsuite/sim/sh64/media/mmacnfx-wl.cgs
sim/testsuite/sim/sh64/media/mmulfxl.cgs
sim/testsuite/sim/sh64/media/mmulfxrpw.cgs
sim/testsuite/sim/sh64/media/mmulfxw.cgs
sim/testsuite/sim/sh64/media/mmulhiwl.cgs
sim/testsuite/sim/sh64/media/mmull.cgs
sim/testsuite/sim/sh64/media/mmullowl.cgs
sim/testsuite/sim/sh64/media/mmulsumwq.cgs
sim/testsuite/sim/sh64/media/mmulw.cgs
sim/testsuite/sim/sh64/media/movi.cgs
sim/testsuite/sim/sh64/media/mpermw.cgs
sim/testsuite/sim/sh64/media/msadubq.cgs
sim/testsuite/sim/sh64/media/mshaldsl.cgs
sim/testsuite/sim/sh64/media/mshaldsw.cgs
sim/testsuite/sim/sh64/media/mshardl.cgs
sim/testsuite/sim/sh64/media/mshardsq.cgs
sim/testsuite/sim/sh64/media/mshardw.cgs
sim/testsuite/sim/sh64/media/mshfhib.cgs
sim/testsuite/sim/sh64/media/mshfhil.cgs
sim/testsuite/sim/sh64/media/mshfhiw.cgs
sim/testsuite/sim/sh64/media/mshflob.cgs
sim/testsuite/sim/sh64/media/mshflol.cgs
sim/testsuite/sim/sh64/media/mshflow.cgs
sim/testsuite/sim/sh64/media/mshlldl.cgs
sim/testsuite/sim/sh64/media/mshlldw.cgs
sim/testsuite/sim/sh64/media/mshlrdl.cgs
sim/testsuite/sim/sh64/media/mshlrdw.cgs
sim/testsuite/sim/sh64/media/msubl.cgs
sim/testsuite/sim/sh64/media/msubsl.cgs
sim/testsuite/sim/sh64/media/msubsub.cgs
sim/testsuite/sim/sh64/media/msubsw.cgs
sim/testsuite/sim/sh64/media/msubw.cgs
sim/testsuite/sim/sh64/media/mulsl.cgs
sim/testsuite/sim/sh64/media/mulul.cgs
sim/testsuite/sim/sh64/media/nop.cgs
sim/testsuite/sim/sh64/media/nsb.cgs
sim/testsuite/sim/sh64/media/ocbi.cgs
sim/testsuite/sim/sh64/media/ocbp.cgs
sim/testsuite/sim/sh64/media/ocbwb.cgs
sim/testsuite/sim/sh64/media/or.cgs
sim/testsuite/sim/sh64/media/ori.cgs
sim/testsuite/sim/sh64/media/prefi.cgs
sim/testsuite/sim/sh64/media/pta.cgs
sim/testsuite/sim/sh64/media/ptabs.cgs
sim/testsuite/sim/sh64/media/ptb.cgs
sim/testsuite/sim/sh64/media/ptrel.cgs
sim/testsuite/sim/sh64/media/putcfg.cgs
sim/testsuite/sim/sh64/media/putcon.cgs
sim/testsuite/sim/sh64/media/rte.cgs
sim/testsuite/sim/sh64/media/shard.cgs
sim/testsuite/sim/sh64/media/shardl.cgs
sim/testsuite/sim/sh64/media/shari.cgs
sim/testsuite/sim/sh64/media/sharil.cgs
sim/testsuite/sim/sh64/media/shlld.cgs
sim/testsuite/sim/sh64/media/shlldl.cgs
sim/testsuite/sim/sh64/media/shlli.cgs
sim/testsuite/sim/sh64/media/shllil.cgs
sim/testsuite/sim/sh64/media/shlrd.cgs
sim/testsuite/sim/sh64/media/shlrdl.cgs
sim/testsuite/sim/sh64/media/shlri.cgs
sim/testsuite/sim/sh64/media/shlril.cgs
sim/testsuite/sim/sh64/media/shori.cgs
sim/testsuite/sim/sh64/media/sleep.cgs
sim/testsuite/sim/sh64/media/stb.cgs
sim/testsuite/sim/sh64/media/sthil.cgs
sim/testsuite/sim/sh64/media/sthiq.cgs
sim/testsuite/sim/sh64/media/stl.cgs
sim/testsuite/sim/sh64/media/stlol.cgs
sim/testsuite/sim/sh64/media/stloq.cgs
sim/testsuite/sim/sh64/media/stq.cgs
sim/testsuite/sim/sh64/media/stw.cgs
sim/testsuite/sim/sh64/media/stxb.cgs
sim/testsuite/sim/sh64/media/stxl.cgs
sim/testsuite/sim/sh64/media/stxq.cgs
sim/testsuite/sim/sh64/media/stxw.cgs
sim/testsuite/sim/sh64/media/sub.cgs
sim/testsuite/sim/sh64/media/subl.cgs
sim/testsuite/sim/sh64/media/swapq.cgs
sim/testsuite/sim/sh64/media/synci.cgs
sim/testsuite/sim/sh64/media/synco.cgs
sim/testsuite/sim/sh64/media/testutils.inc
sim/testsuite/sim/sh64/media/trapa.cgs
sim/testsuite/sim/sh64/media/xor.cgs
sim/testsuite/sim/sh64/media/xori.cgs
sim/testsuite/sim/sh64/misc/fr-dr.s
Diffstat (limited to 'cpu')
| -rw-r--r-- | cpu/ChangeLog | 54 | ||||
| -rw-r--r-- | cpu/frv.opc | 58 | ||||
| -rw-r--r-- | cpu/m32c.cpu | 392 | ||||
| -rw-r--r-- | cpu/m32c.opc | 66 | ||||
| -rw-r--r-- | cpu/m32r.opc | 8 |
5 files changed, 386 insertions, 192 deletions
diff --git a/cpu/ChangeLog b/cpu/ChangeLog index 0d8f21d..1fc6255 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,3 +1,57 @@ +2005-10-28 Dave Brolley <brolley@redhat.com> + + Contribute the following change: + 2003-09-24 Dave Brolley <brolley@redhat.com> + + * frv.opc: Use CGEN_ATTR_VALUE_ENUM_TYPE in place of + CGEN_ATTR_VALUE_TYPE. + * m32c.opc (m32c_cgen_insn_supported): Use CGEN_INSN_BITSET_ATTR_VALUE. + Use cgen_bitset_intersect_p. + +2005-10-27 DJ Delorie <dj@redhat.com> + + * m32c.cpu (Imm-8-s4n, Imm-12-s4n): New. + (arith-jnz16-imm4-dst-defn, arith-jnz32-imm4-dst-defn, + arith-jnz-imm4-dst-mach, arith-jnz-imm4-dst): Keep track of which + imm operand is needed. + (adjnz, sbjnz): Pass the right operands. + (unary-insn-defn, unary16-defn, unary32-defn, unary-insn-mach, + unary-insn): Add -g variants for opcodes that need to support :G. + (not.BW:G, push.BW:G): Call it. + (stzx16-imm8-imm8-dsp8sb, stzx16-imm8-imm8-dsp8fb, + stzx16-imm8-imm8-abs16): Fix operand typos. + * m32c.opc (m32c_asm_hash): Support bnCND. + (parse_signed4n, print_signed4n): New. + +2005-10-26 DJ Delorie <dj@redhat.com> + + * m32c.cpu (f-dsp-8-s24, Dsp-8-s24): New. + (mov-dspsp-dst-defn, mov-src-dspsp-defn, mov16-dspsp-dst-defn, + mov16-src-dspsp-defn, mov32-dspsp-dst-defn, mov32-src-dspsp-defn): + dsp8[sp] is signed. + (mov.WL:S #imm,A0/A1): dsp24 is signed (i.e. -0x800000..0xffffff). + (mov.BW:S r0,r1): Fix typo r1l->r1. + (tst): Allow :G suffix. + * m32c.opc (parse_signed24): New, for -0x800000..0xffffff. + +2005-10-26 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> + + * m32r.opc (parse_hi16): Do not assume a 32-bit host word size. + +2005-10-25 DJ Delorie <dj@redhat.com> + + * m32c.cpu (add16-bQ-sp,add16-wQ-sp): Fix to allow either width by + making one a macro of the other. + +2005-10-21 DJ Delorie <dj@redhat.com> + + * m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing. + (indexb, indexbd, indexbs, indexw, indexwd, indexws, indexl, + indexld, indexls): .w variants have `1' bit. + (rot32.b): QI, not SI. + (rot32.w): HI, not SI. + (xchg16): HI for .w variant. + 2005-10-19 Nick Clifton <nickc@redhat.com> * m32r.opc (parse_slo16): Fix bad application of previous patch. diff --git a/cpu/frv.opc b/cpu/frv.opc index c3e8405..5d2dc89 100644 --- a/cpu/frv.opc +++ b/cpu/frv.opc @@ -50,7 +50,7 @@ #define FRV_VLIW_SIZE 8 /* fr550 has largest vliw size of 8. */ #define PAD_VLIW_COMBO ,UNIT_NIL,UNIT_NIL,UNIT_NIL,UNIT_NIL -typedef CGEN_ATTR_VALUE_TYPE VLIW_COMBO[FRV_VLIW_SIZE]; +typedef CGEN_ATTR_VALUE_ENUM_TYPE VLIW_COMBO[FRV_VLIW_SIZE]; typedef struct { @@ -58,15 +58,15 @@ typedef struct int constraint_violation; unsigned long mach; unsigned long elf_flags; - CGEN_ATTR_VALUE_TYPE * unit_mapping; + CGEN_ATTR_VALUE_ENUM_TYPE * unit_mapping; VLIW_COMBO * current_vliw; - CGEN_ATTR_VALUE_TYPE major[FRV_VLIW_SIZE]; + CGEN_ATTR_VALUE_ENUM_TYPE major[FRV_VLIW_SIZE]; const CGEN_INSN * insn[FRV_VLIW_SIZE]; } FRV_VLIW; -int frv_is_branch_major (CGEN_ATTR_VALUE_TYPE, unsigned long); -int frv_is_float_major (CGEN_ATTR_VALUE_TYPE, unsigned long); -int frv_is_media_major (CGEN_ATTR_VALUE_TYPE, unsigned long); +int frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long); +int frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long); +int frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE, unsigned long); int frv_is_branch_insn (const CGEN_INSN *); int frv_is_float_insn (const CGEN_INSN *); int frv_is_media_insn (const CGEN_INSN *); @@ -83,7 +83,7 @@ int spr_valid (long); development tree. */ bfd_boolean -frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) +frv_is_branch_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach) { switch (mach) { @@ -107,7 +107,7 @@ frv_is_branch_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) /* Returns TRUE if {MAJOR,MACH} supports floating point insns. */ bfd_boolean -frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) +frv_is_float_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach) { switch (mach) { @@ -126,7 +126,7 @@ frv_is_float_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) /* Returns TRUE if {MAJOR,MACH} supports media insns. */ bfd_boolean -frv_is_media_major (CGEN_ATTR_VALUE_TYPE major, unsigned long mach) +frv_is_media_major (CGEN_ATTR_VALUE_ENUM_TYPE major, unsigned long mach) { switch (mach) { @@ -270,7 +270,7 @@ static VLIW_COMBO fr550_allowed_vliw[] = /* Some insns are assigned specialized implementation units which map to different actual implementation units on different machines. These tables perform that mapping. */ -static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] = +static CGEN_ATTR_VALUE_ENUM_TYPE fr400_unit_mapping[] = { /* unit in insn actual unit */ /* NIL */ UNIT_NIL, @@ -305,7 +305,7 @@ static CGEN_ATTR_VALUE_TYPE fr400_unit_mapping[] = /* Some insns are assigned specialized implementation units which map to different actual implementation units on different machines. These tables perform that mapping. */ -static CGEN_ATTR_VALUE_TYPE fr450_unit_mapping[] = +static CGEN_ATTR_VALUE_ENUM_TYPE fr450_unit_mapping[] = { /* unit in insn actual unit */ /* NIL */ UNIT_NIL, @@ -337,7 +337,7 @@ static CGEN_ATTR_VALUE_TYPE fr450_unit_mapping[] = /* MCLRACC-1*/ UNIT_FM0 /* mclracc,A==1 insn only in FM0 unit. */ }; -static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] = +static CGEN_ATTR_VALUE_ENUM_TYPE fr500_unit_mapping[] = { /* unit in insn actual unit */ /* NIL */ UNIT_NIL, @@ -369,7 +369,7 @@ static CGEN_ATTR_VALUE_TYPE fr500_unit_mapping[] = /* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */ }; -static CGEN_ATTR_VALUE_TYPE fr550_unit_mapping[] = +static CGEN_ATTR_VALUE_ENUM_TYPE fr550_unit_mapping[] = { /* unit in insn actual unit */ /* NIL */ UNIT_NIL, @@ -435,7 +435,7 @@ frv_vliw_reset (FRV_VLIW *vliw, unsigned long mach, unsigned long elf_flags) *_allowed_vliw tables above. */ static bfd_boolean match_unit (FRV_VLIW *vliw, - CGEN_ATTR_VALUE_TYPE unit1, CGEN_ATTR_VALUE_TYPE unit2) + CGEN_ATTR_VALUE_ENUM_TYPE unit1, CGEN_ATTR_VALUE_ENUM_TYPE unit2) { /* Map any specialized implementation units to actual ones. */ unit1 = vliw->unit_mapping[unit1]; @@ -487,7 +487,7 @@ match_vliw (VLIW_COMBO *vliw1, VLIW_COMBO *vliw2, int vliw_size) If one is found then return it. Otherwise return NULL. */ static VLIW_COMBO * -add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit) +add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE unit) { int next = vliw->next_slot; VLIW_COMBO *current = vliw->current_vliw; @@ -518,7 +518,7 @@ add_next_to_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit) Returns TRUE if found, FALSE otherwise. */ static bfd_boolean -find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) +find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major) { int i; @@ -533,7 +533,7 @@ find_major_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) types. */ static bfd_boolean -fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) +fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major) { /* In the cpu file, all media insns are represented as being allowed in both media units. This makes it easier since this is the case for fr500. @@ -553,9 +553,9 @@ fr400_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) } static bfd_boolean -fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) +fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major) { - CGEN_ATTR_VALUE_TYPE other_major; + CGEN_ATTR_VALUE_ENUM_TYPE other_major; /* Our caller guarantees there's at least one other instruction. */ other_major = CGEN_INSN_ATTR_VALUE (vliw->insn[0], CGEN_INSN_FR450_MAJOR); @@ -588,7 +588,7 @@ fr450_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) } static bfd_boolean -find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit) +find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE unit) { int i; @@ -601,8 +601,8 @@ find_unit_in_vliw (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit) static bfd_boolean find_major_in_slot (FRV_VLIW *vliw, - CGEN_ATTR_VALUE_TYPE major, - CGEN_ATTR_VALUE_TYPE slot) + CGEN_ATTR_VALUE_ENUM_TYPE major, + CGEN_ATTR_VALUE_ENUM_TYPE slot) { int i; @@ -657,11 +657,11 @@ fr550_find_float_in_vliw (FRV_VLIW *vliw) static bfd_boolean fr550_check_insn_major_constraints (FRV_VLIW *vliw, - CGEN_ATTR_VALUE_TYPE major, + CGEN_ATTR_VALUE_ENUM_TYPE major, const CGEN_INSN *insn) { - CGEN_ATTR_VALUE_TYPE unit; - CGEN_ATTR_VALUE_TYPE slot = (*vliw->current_vliw)[vliw->next_slot]; + CGEN_ATTR_VALUE_ENUM_TYPE unit; + CGEN_ATTR_VALUE_ENUM_TYPE slot = (*vliw->current_vliw)[vliw->next_slot]; switch (slot) { case UNIT_I2: @@ -707,7 +707,7 @@ fr550_check_insn_major_constraints (FRV_VLIW *vliw, } static bfd_boolean -fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) +fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_ENUM_TYPE major) { /* TODO: A table might be faster for some of the more complex instances here. */ @@ -815,7 +815,7 @@ fr500_check_insn_major_constraints (FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major) static bfd_boolean check_insn_major_constraints (FRV_VLIW *vliw, - CGEN_ATTR_VALUE_TYPE major, + CGEN_ATTR_VALUE_ENUM_TYPE major, const CGEN_INSN *insn) { switch (vliw->mach) @@ -841,8 +841,8 @@ int frv_vliw_add_insn (FRV_VLIW *vliw, const CGEN_INSN *insn) { int index; - CGEN_ATTR_VALUE_TYPE major; - CGEN_ATTR_VALUE_TYPE unit; + CGEN_ATTR_VALUE_ENUM_TYPE major; + CGEN_ATTR_VALUE_ENUM_TYPE unit; VLIW_COMBO *new_vliw; if (vliw->constraint_violation || CGEN_INSN_INVALID_P (insn)) diff --git a/cpu/m32c.cpu b/cpu/m32c.cpu index 095e7cd..cb892ff 100644 --- a/cpu/m32c.cpu +++ b/cpu/m32c.cpu @@ -557,6 +557,15 @@ (and UHI (srl UHI value 8) #x00ff) (and UHI (sll UHI value 8) #xff00))) ; extract ) +(df f-dsp-8-s24 "24 bit signed" (all-isas) 8 24 INT + ((value pc) (or SI + (or (srl value 16) (and value #xff00)) + (sll (ext INT (trunc QI (and value #xff))) 16))) + ((value pc) (or SI + (or (srl value 16) (and value #xff00)) + (sll (ext INT (trunc QI (and value #xff))) 16))) + ) + (df f-dsp-8-u24 "24 bit unsigned" (all-isas) 8 24 UINT ((value pc) (or SI (or (srl value 16) (and value #xff00)) @@ -1756,6 +1765,10 @@ h-sint DFLT f-dsp-8-s8 ((parse "signed8")) () () ) +(define-full-operand Dsp-8-s24 "signed 24 bit displacement at offset 8 bits" (all-isas) + h-sint DFLT f-dsp-8-s24 + ((parse "signed24")) () () +) (define-full-operand Dsp-8-u24 "unsigned 24 bit displacement at offset 8 bits" (all-isas) h-uint DFLT f-dsp-8-u24 ((parse "unsigned24")) () () @@ -1881,6 +1894,10 @@ h-sint DFLT f-imm-8-s4 ((parse "signed4")) () () ) +(define-full-operand Imm-8-s4n "negated 4 bit immediate at offset 8 bits" (all-isas) + h-sint DFLT f-imm-8-s4 + ((parse "signed4n")) () () +) (define-full-operand Imm-sh-8-s4 "signed 4 bit shift immediate at offset 8 bits" (all-isas) h-shimm DFLT f-imm-8-s4 () () () @@ -1897,6 +1914,10 @@ h-sint DFLT f-imm-12-s4 ((parse "signed4")) () () ) +(define-full-operand Imm-12-s4n "negated 4 bit immediate at offset 12 bits" (all-isas) + h-sint DFLT f-imm-12-s4 + ((parse "signed4n") (print "signed4n")) () () +) (define-full-operand Imm-sh-12-s4 "signed 4 bit shift immediate at offset 12 bits" (all-isas) h-shimm DFLT f-imm-12-s4 () () () @@ -5835,24 +5856,31 @@ ; Unary insn macros ;------------------------------------------------------------- -(define-pmacro (unary-insn-defn mach group mode wstr op encoding sem) +(define-pmacro (unary-insn-defn-g mach group mode wstr op encoding sem opg) (dni (.sym op mach wstr - group) - (.str op wstr " dst" mach "-" group "-" mode) + (.str op wstr opg " dst" mach "-" group "-" mode) ((machine mach)) - (.str op wstr " ${dst" mach "-" group "-" mode "}") + (.str op wstr opg " ${dst" mach "-" group "-" mode "}") encoding (sem mode (.sym dst mach - group - mode)) ()) ) +(define-pmacro (unary-insn-defn mach group mode wstr op encoding sem) + (unary-insn-defn-g mach group mode wstr op encoding sem "") +) + +(define-pmacro (unary16-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg) + (unary-insn-defn-g 16 16 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16- mode)) + sem opg) +) (define-pmacro (unary16-defn mode wstr wbit op opc1 opc2 opc3 sem) - (unary-insn-defn 16 16 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16- mode)) - sem) + (unary-16-defn-g mode wstr wbit op opc1 opc2 opc3 sem "") ) -(define-pmacro (unary32-defn mode wstr wbit op opc1 opc2 opc3 sem) +(define-pmacro (unary32-defn-g mode wstr wbit op opc1 opc2 opc3 sem opg) (begin ; Multi insns are tried for assembly in the reverse order in which they appear here, so ; define the absolute-indirect insns first in order to prevent them from being selected @@ -5860,26 +5888,39 @@ ; (unary-insn-defn 32 24-absolute-indirect mode wstr op ; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-absolute-indirect- mode) (f-18-2 opc2) (f-20-4 opc3)) ; sem) - (unary-insn-defn 32 16-Unprefixed mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3)) - sem) + (unary-insn-defn-g 32 16-Unprefixed mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3)) + sem opg) ; (unary-insn-defn 32 24-indirect mode wstr op ; (+ (f-0-4 0) (f-4-4 9) (f-8-4 opc1) (f-15-1 wbit) (.sym dst32-24-indirect- mode) (f-18-2 opc2) (f-20-4 opc3)) ; sem) ) ) +(define-pmacro (unary32-defn mode wstr wbit op opc1 opc2 opc3 sem) + (unary32-defn-g mode wstr wbit op opc1 opc2 opc3 sem "") +) -(define-pmacro (unary-insn-mach mach op opc1 opc2 opc3 sem) +(define-pmacro (unary-insn-mach-g mach op opc1 opc2 opc3 sem opg) (begin - (.apply (.sym unary mach -defn) (QI .b 0 op opc1 opc2 opc3 sem)) - (.apply (.sym unary mach -defn) (HI .w 1 op opc1 opc2 opc3 sem)) + (.apply (.sym unary mach -defn-g) (QI .b 0 op opc1 opc2 opc3 sem opg)) + (.apply (.sym unary mach -defn-g) (HI .w 1 op opc1 opc2 opc3 sem opg)) ) ) +(define-pmacro (unary-insn-mach mach op opc1 opc2 opc3 sem) + (unary-insn-mach-g mach op opc1 opc2 opc3 sem "") +) (define-pmacro (unary-insn op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) (begin - (unary-insn-mach 16 op opc16-1 opc16-2 opc16-3 sem) - (unary-insn-mach 32 op opc32-1 opc32-2 opc32-3 sem) + (unary-insn-mach-g 16 op opc16-1 opc16-2 opc16-3 sem "") + (unary-insn-mach-g 32 op opc32-1 opc32-2 opc32-3 sem "") + ) +) + +(define-pmacro (unary-insn-g op opc16-1 opc16-2 opc16-3 opc32-1 opc32-2 opc32-3 sem) + (begin + (unary-insn-mach-g 16 op opc16-1 opc16-2 opc16-3 sem "$G") + (unary-insn-mach-g 32 op opc32-1 opc32-2 opc32-3 sem "$G") ) ) @@ -5997,10 +6038,10 @@ ;------------------------------------------------------------- (define-pmacro (binary-arith16-Q-sp op opc1 opc2 opc3 sem) - (dni (.sym op 16 -Q-sp) - (.str op ":Q #imm4,sp") + (dni (.sym op 16 -wQ-sp) + (.str op ".w:q #imm4,sp") ((machine 16)) - (.str op "${size}$Q #${Imm-12-s4},sp") + (.str op ".w$Q #${Imm-12-s4},sp") (+ opc1 opc2 opc3 Imm-12-s4) (sem QI Imm-12-s4 sp) ()) @@ -6542,49 +6583,49 @@ ) ; m16c variants -(define-pmacro (arith-jnz16-imm4-dst-defn mode wstr wbit op opc1 opc2 sem) +(define-pmacro (arith-jnz16-imm4-dst-defn mode wstr wbit op i4n opc1 opc2 sem) (begin - (arith-jnz-imm4-dst-defn 16 Imm-8-s4 basic Lab-16-8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) Imm-8-s4 (.sym dst16-basic- mode) Lab-16-8) + (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) basic Lab-16-8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-basic- mode) Lab-16-8) sem) - (arith-jnz-imm4-dst-defn 16 Imm-8-s4 16-16 Lab-32-8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) Imm-8-s4 (.sym dst16-16-16- mode) Lab-16-8) + (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-16 Lab-32-8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-16- mode) Lab-16-8) sem) - (arith-jnz-imm4-dst-defn 16 Imm-8-s4 16-8 Lab-24-8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) Imm-8-s4 (.sym dst16-16-8- mode) Lab-16-8) + (arith-jnz-imm4-dst-defn 16 (.sym Imm-8- i4n) 16-8 Lab-24-8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) (.sym Imm-8- i4n) (.sym dst16-16-8- mode) Lab-16-8) sem) ) ) ; m32c variants -(define-pmacro (arith-jnz32-imm4-dst-defn mode wstr wbit op opc1 opc2 sem) +(define-pmacro (arith-jnz32-imm4-dst-defn mode wstr wbit op i4n opc1 opc2 sem) (begin - (arith-jnz-imm4-dst-defn 32 Imm-12-s4 basic-Unprefixed Lab-16-8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4 Lab-16-8) + (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) basic-Unprefixed Lab-16-8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-16-8) sem) - (arith-jnz-imm4-dst-defn 32 Imm-12-s4 16-24-Unprefixed Lab-40-8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4 Lab-40-8) + (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-24-Unprefixed Lab-40-8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-40-8) sem) - (arith-jnz-imm4-dst-defn 32 Imm-12-s4 16-16-Unprefixed Lab-32-8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4 Lab-32-8) + (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-16-Unprefixed Lab-32-8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-32-8) sem) - (arith-jnz-imm4-dst-defn 32 Imm-12-s4 16-8-Unprefixed Lab-24-8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) Imm-12-s4 Lab-24-8) + (arith-jnz-imm4-dst-defn 32 (.sym Imm-12- i4n) 16-8-Unprefixed Lab-24-8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (.sym Imm-12- i4n) Lab-24-8) sem) ) ) -(define-pmacro (arith-jnz-imm4-dst-mach mach op opc1 opc2 sem) +(define-pmacro (arith-jnz-imm4-dst-mach mach op i4n opc1 opc2 sem) (begin - (.apply (.sym arith-jnz mach -imm4-dst-defn) (QI .b 0 op opc1 opc2 sem)) - (.apply (.sym arith-jnz mach -imm4-dst-defn) (HI .w 1 op opc1 opc2 sem)) + (.apply (.sym arith-jnz mach -imm4-dst-defn) (QI .b 0 op i4n opc1 opc2 sem)) + (.apply (.sym arith-jnz mach -imm4-dst-defn) (HI .w 1 op i4n opc1 opc2 sem)) ) ) -(define-pmacro (arith-jnz-imm4-dst op opc16-1 opc16-2 opc32-1 opc32-2 sem) +(define-pmacro (arith-jnz-imm4-dst op i4n opc16-1 opc16-2 opc32-1 opc32-2 sem) (begin - (arith-jnz-imm4-dst-mach 16 op opc16-1 opc16-2 sem) - (arith-jnz-imm4-dst-mach 32 op opc32-1 opc32-2 sem) + (arith-jnz-imm4-dst-mach 16 op i4n opc16-1 opc16-2 sem) + (arith-jnz-imm4-dst-mach 32 op i4n opc32-1 opc32-2 sem) ) ) @@ -6595,7 +6636,7 @@ (dni (.sym op mach wstr -dspsp-dst- dstgroup) (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode) ((machine mach)) - (.str op wstr " ${" dsp "}[sp],${dst" mach "-" dstgroup "-" mode "}") + (.str op wstr "$G ${" dsp "}[sp],${dst" mach "-" dstgroup "-" mode "}") encoding (sem mach mode dsp (.sym dst mach - dstgroup - mode)) ()) @@ -6604,7 +6645,7 @@ (dni (.sym op mach wstr -dst-dspsp- dstgroup) (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode) ((machine mach)) - (.str op wstr " ${dst" mach "-" dstgroup "-" mode "},${" dsp "}[sp]") + (.str op wstr "$G ${dst" mach "-" dstgroup "-" mode "},${" dsp "}[sp]") encoding (sem mach mode (.sym dst mach - dstgroup - mode) dsp) ()) @@ -6613,28 +6654,28 @@ ; m16c variants (define-pmacro (mov16-dspsp-dst-defn mode wstr wbit op opc1 opc2 opc3 sem) (begin - (mov-dspsp-dst-defn 16 basic Dsp-16-u8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-u8) + (mov-dspsp-dst-defn 16 basic Dsp-16-s8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-s8) sem) - (mov-dspsp-dst-defn 16 16-16 Dsp-32-u8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-u8) + (mov-dspsp-dst-defn 16 16-16 Dsp-32-s8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-s8) sem) - (mov-dspsp-dst-defn 16 16-8 Dsp-24-u8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-u8) + (mov-dspsp-dst-defn 16 16-8 Dsp-24-s8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-s8) sem) ) ) (define-pmacro (mov16-src-dspsp-defn mode wstr wbit op opc1 opc2 opc3 sem) (begin - (mov-src-dspsp-defn 16 basic Dsp-16-u8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-u8) + (mov-src-dspsp-defn 16 basic Dsp-16-s8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-s8) sem) - (mov-src-dspsp-defn 16 16-16 Dsp-32-u8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-u8) + (mov-src-dspsp-defn 16 16-16 Dsp-32-s8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-s8) sem) - (mov-src-dspsp-defn 16 16-8 Dsp-24-u8 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-u8) + (mov-src-dspsp-defn 16 16-8 Dsp-24-s8 mode wstr op + (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-s8) sem) ) ) @@ -6642,33 +6683,33 @@ ; m32c variants (define-pmacro (mov32-dspsp-dst-defn mode wstr wbit op opc1 opc2 opc3 sem) (begin - (mov-dspsp-dst-defn 32 basic-Unprefixed Dsp-16-u8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-u8) + (mov-dspsp-dst-defn 32 basic-Unprefixed Dsp-16-s8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-s8) sem) - (mov-dspsp-dst-defn 32 16-24-Unprefixed Dsp-40-u8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-u8) + (mov-dspsp-dst-defn 32 16-24-Unprefixed Dsp-40-s8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-s8) sem) - (mov-dspsp-dst-defn 32 16-16-Unprefixed Dsp-32-u8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-u8) + (mov-dspsp-dst-defn 32 16-16-Unprefixed Dsp-32-s8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-s8) sem) - (mov-dspsp-dst-defn 32 16-8-Unprefixed Dsp-24-u8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-u8) + (mov-dspsp-dst-defn 32 16-8-Unprefixed Dsp-24-s8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-s8) sem) ) ) (define-pmacro (mov32-src-dspsp-defn mode wstr wbit op opc1 opc2 opc3 sem) (begin - (mov-src-dspsp-defn 32 basic-Unprefixed Dsp-16-u8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-u8) + (mov-src-dspsp-defn 32 basic-Unprefixed Dsp-16-s8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-basic-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-16-s8) sem) - (mov-src-dspsp-defn 32 16-24-Unprefixed Dsp-40-u8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-u8) + (mov-src-dspsp-defn 32 16-24-Unprefixed Dsp-40-s8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-24-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-40-s8) sem) - (mov-src-dspsp-defn 32 16-16-Unprefixed Dsp-32-u8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-u8) + (mov-src-dspsp-defn 32 16-16-Unprefixed Dsp-32-s8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-16-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-32-s8) sem) - (mov-src-dspsp-defn 32 16-8-Unprefixed Dsp-24-u8 mode wstr op - (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-u8) + (mov-src-dspsp-defn 32 16-8-Unprefixed Dsp-24-s8 mode wstr op + (+ (f-0-4 opc1) (f-7-1 wbit) (.sym dst32-16-8-Unprefixed- mode) (f-10-2 opc2) (f-12-4 opc3) Dsp-24-s8) sem) ) ) @@ -6702,59 +6743,91 @@ ;------------------------------------------------------------- ; lde dsp24,dst -- for m16c -; TODO abs20[a0], [a0a1] for dsp24 ;------------------------------------------------------------- -(define-pmacro (lde-defn mach dstgroup dsp mode wstr op encoding sem) - (dni (.sym op mach wstr -dst-dspsp- dstgroup) - (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode) - ((machine mach)) - (.str op wstr " ${" dsp "},${dst" mach "-" dstgroup "-" mode "}") - encoding - (sem mode (.sym dst mach - dstgroup - mode) dsp) - ()) -) +(define-pmacro (lde-dst-dsp mode wstr wbit dstgroup srcdisp) + (begin + + (dni (.sym lde wstr - dstgroup -u20) + (.str "lde" wstr "-" dstgroup "-u20") + ((machine 16)) + (.str "lde" wstr " ${" srcdisp "},${dst16-" dstgroup "-" mode "}") + (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x8) + (.sym dst16- dstgroup - mode) srcdisp) + (nop) + ()) -(define-pmacro (lde-dst mode wstr wbit op opc1 opc2 opc3 sem) + (dni (.sym lde wstr - dstgroup -u20a0) + (.str "lde" wstr "-" dstgroup "-u20a0") + ((machine 16)) + (.str "lde" wstr " ${" srcdisp "}[a0],${dst16-" dstgroup "-" mode "}") + (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x9) + (.sym dst16- dstgroup - mode) srcdisp) + (nop) + ()) + + (dni (.sym lde wstr - dstgroup -a1a0) + (.str "lde" wstr "-" dstgroup "-a1a0") + ((machine 16)) + (.str "lde" wstr " [a1a0],${dst16-" dstgroup "-" mode "}") + (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #xa) + (.sym dst16- dstgroup - mode)) + (nop) + ()) + ) + ) + +(define-pmacro (lde-dst mode wstr wbit) (begin - (lde-defn 16 basic Dsp-16-u20 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-u20) - sem) - (lde-defn 16 16-16 Dsp-32-u20 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-u20) - sem) - (lde-defn 16 16-8 Dsp-24-u20 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-u20) - sem) + ; like: QI .b 0 + (lde-dst-dsp mode wstr wbit basic Dsp-16-u20) + (lde-dst-dsp mode wstr wbit 16-8 Dsp-24-u20) + (lde-dst-dsp mode wstr wbit 16-16 Dsp-32-u20) ) ) ;------------------------------------------------------------- -; ste src,dsp24 -- for m16c -; TODO abs20[a0], [a0a1] for dsp24 +; ste dst,dsp24 -- for m16c ;------------------------------------------------------------- -(define-pmacro (ste-defn mach dstgroup dsp mode wstr op encoding sem) - (dni (.sym op mach wstr -dst-dspsp- dstgroup) - (.str op wstr " " mach "-dsp[sp]-" dstgroup "-" dsp "-" mode) - ((machine mach)) - (.str op wstr " ${dst" mach "-" dstgroup "-" mode "},${" dsp "}") - encoding - (sem mode (.sym dst mach - dstgroup - mode) dsp) - ()) -) +(define-pmacro (ste-dst-dsp mode wstr wbit dstgroup srcdisp) + (begin + + (dni (.sym ste wstr - dstgroup -u20) + (.str "ste" wstr "-" dstgroup "-u20") + ((machine 16)) + (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}") + (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x0) + (.sym dst16- dstgroup - mode) srcdisp) + (nop) + ()) + + (dni (.sym ste wstr - dstgroup -u20a0) + (.str "ste" wstr "-" dstgroup "-u20a0") + ((machine 16)) + (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},${" srcdisp "}[a0]") + (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x1) + (.sym dst16- dstgroup - mode) srcdisp) + (nop) + ()) + + (dni (.sym ste wstr - dstgroup -a1a0) + (.str "ste" wstr "-" dstgroup "-a1a0") + ((machine 16)) + (.str "ste" wstr " ${dst16-" dstgroup "-" mode "},[a1a0]") + (+ (f-0-4 #x7) (f-4-3 #x2) (f-7-1 wbit) (f-8-4 #x2) + (.sym dst16- dstgroup - mode)) + (nop) + ()) + ) + ) -(define-pmacro (ste-dst mode wstr wbit op opc1 opc2 opc3 sem) +(define-pmacro (ste-dst mode wstr wbit) (begin - (ste-defn 16 basic Dsp-16-u20 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-basic- mode) Dsp-16-u20) - sem) - (ste-defn 16 16-16 Dsp-32-u20 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-16- mode) Dsp-32-u20) - sem) - (ste-defn 16 16-8 Dsp-24-u20 mode wstr op - (+ opc1 opc2 (f-7-1 wbit) opc3 (.sym dst16-16-8- mode) Dsp-24-u20) - sem) + ; like: QI .b 0 + (ste-dst-dsp mode wstr wbit basic Dsp-16-u20) + (ste-dst-dsp mode wstr wbit 16-8 Dsp-24-u20) + (ste-dst-dsp mode wstr wbit 16-16 Dsp-32-u20) ) ) @@ -7091,6 +7164,9 @@ (binary-arith16-b-S-imm8-dst3 add ".b" (f-0-4 8) (f-4-1 0) add-sem) ; add.BW:Q #imm4,sp (m16 #7) (binary-arith16-Q-sp add (f-0-4 7) (f-4-4 #xD) (f-8-4 #xB) add-sem) +(dnmi add16-bQ-sp "add16-bQ-sp" () + "add.b:q #${Imm-12-s4},sp" + (emit add16-wQ-sp Imm-12-s4)) ; add.BW:G #imm,sp (m16 #6) (binary-arith16-G-sp add (f-0-4 7) (f-4-3 6) (f-8-4 #xE) (f-12-4 #xB) add-sem) ; add.BW:G src,dst (m16 #4 m32 #6) @@ -7246,7 +7322,7 @@ ) ; adjnz.size #imm4,dst,label -(arith-jnz-imm4-dst adjnz (f-0-4 #xF) (f-4-3 4) #xf #x1 arith-jnz-sem) +(arith-jnz-imm4-dst adjnz s4 (f-0-4 #xF) (f-4-3 4) #xf #x1 arith-jnz-sem) ;------------------------------------------------------------- ; and - binary and @@ -7905,31 +7981,31 @@ ; indexb src (index byte) (unary32-defn QI .b 0 indexb #x8 0 #x3 indexb-sem) -(unary32-defn HI .w 0 indexb #x8 1 #x3 indexb-sem) +(unary32-defn HI .w 1 indexb #x8 1 #x3 indexb-sem) ; indexbd src (index byte dest) (unary32-defn QI .b 0 indexbd #xA 0 3 indexbd-sem) -(unary32-defn HI .w 0 indexbd #xA 1 3 indexbd-sem) +(unary32-defn HI .w 1 indexbd #xA 1 3 indexbd-sem) ; indexbs src (index byte src) (unary32-defn QI .b 0 indexbs #xC 0 3 indexbs-sem) -(unary32-defn HI .w 0 indexbs #xC 1 3 indexbs-sem) +(unary32-defn HI .w 1 indexbs #xC 1 3 indexbs-sem) ; indexl src (index long) (unary32-defn QI .b 0 indexl 9 2 3 indexl-sem) -(unary32-defn HI .w 0 indexl 9 3 3 indexl-sem) +(unary32-defn HI .w 1 indexl 9 3 3 indexl-sem) ; indexld src (index long dest) (unary32-defn QI .b 0 indexld #xB 2 3 indexld-sem) -(unary32-defn HI .w 0 indexld #xB 3 3 indexld-sem) +(unary32-defn HI .w 1 indexld #xB 3 3 indexld-sem) ; indexls src (index long src) (unary32-defn QI .b 0 indexls 9 0 3 indexls-sem) -(unary32-defn HI .w 0 indexls 9 1 3 indexls-sem) +(unary32-defn HI .w 1 indexls 9 1 3 indexls-sem) ; indexw src (index word) (unary32-defn QI .b 0 indexw 8 2 3 indexw-sem) -(unary32-defn HI .w 0 indexw 8 3 3 indexw-sem) +(unary32-defn HI .w 1 indexw 8 3 3 indexw-sem) ; indexwd src (index word dest) (unary32-defn QI .b 0 indexwd #xA 2 3 indexwd-sem) -(unary32-defn HI .w 0 indexwd #xA 3 3 indexwd-sem) +(unary32-defn HI .w 1 indexwd #xA 3 3 indexwd-sem) ; indexws (index word src) (unary32-defn QI .b 0 indexws #xC 2 3 indexws-sem) -(unary32-defn HI .w 0 indexws #xC 3 3 indexws-sem) +(unary32-defn HI .w 1 indexws #xC 3 3 indexws-sem) ;------------------------------------------------------------- ; jcc - jump on condition @@ -8450,21 +8526,11 @@ ; ste - store to extra far data area (m16) ;------------------------------------------------------------- -; A special variant of mem16 for lde and ste -(define-pmacro (extra-mem16 mode address) - (mem mode (and #xfffff address))) +(lde-dst QI .b 0) +(lde-dst HI .w 1) -(define-pmacro (lde-sem mode src1 dst) - (set mode src1 (extra-mem16 mode dst)) -) -(lde-dst QI .b 0 lde (f-0-4 #x7) (f-4-3 2) (f-8-4 #x8) lde-sem) -(lde-dst HI .w 1 lde (f-0-4 #x7) (f-4-3 2) (f-8-4 #x8) lde-sem) - -(define-pmacro (ste-sem mode src1 dst) - (set (extra-mem16 mode dst) src1) -) -(ste-dst QI .b 0 ste (f-0-4 #x7) (f-4-3 2) (f-8-4 #x0) ste-sem) -(ste-dst HI .w 1 ste (f-0-4 #x7) (f-4-3 2) (f-8-4 #x0) ste-sem) +(ste-dst QI .b 0) +(ste-dst HI .w 1) ;------------------------------------------------------------- ; ldipl - load interrupt permission level @@ -8575,8 +8641,8 @@ ) (mov32-wl-s-defn HI w #x9 Imm-8-HI a0 #xC) (mov32-wl-s-defn HI w #x9 Imm-8-HI a1 #xD) -(mov32-wl-s-defn SI l #xB Dsp-8-u24 a0 #xC) -(mov32-wl-s-defn SI l #xB Dsp-8-u24 a1 #xD) +(mov32-wl-s-defn SI l #xB Dsp-8-s24 a0 #xC) +(mov32-wl-s-defn SI l #xB Dsp-8-s24 a1 #xD) ; mov.size:Q #imm4,dst (m16 #2 m32 #3) (binary-arith16-imm4-dst-defn QI .b 0 0 mov (f-0-4 #xD) (f-4-3 4) mov-sem) @@ -8649,7 +8715,7 @@ (mov32-src-r b 0 QI dst32-2-S-8 r0l 0 4) (mov32-src-r w 1 HI dst32-2-S-8 r0 0 4) (mov32-src-r b 0 QI dst32-2-S-basic r1l 1 7) -(mov32-src-r w 1 HI dst32-2-S-basic r1l 1 7) +(mov32-src-r w 1 HI dst32-2-S-basic r1 1 7) (mov32-src-r b 0 QI dst32-2-S-16 r1l 1 7) (mov32-src-r w 1 HI dst32-2-S-16 r1 1 7) (mov32-src-r b 0 QI dst32-2-S-8 r1l 1 7) @@ -8890,7 +8956,15 @@ ) ; not.BW:G -(unary-insn not (f-0-4 7) (f-4-3 2) (f-8-4 #x7) #xA #x1 #xE not-sem) +(unary-insn-g not (f-0-4 7) (f-4-3 2) (f-8-4 #x7) #xA #x1 #xE not-sem) + +(dni not16.b.s + "not.b:s Dst16-3-S-8" + ((machine 16)) + "not.b:s ${Dst16-3-S-8}" + (+ (f-0-4 #xb) (f-4-1 #x1) Dst16-3-S-8) + (not-sem QI Dst16-3-S-8) + ()) ;------------------------------------------------------------- ; nop @@ -9279,7 +9353,7 @@ ()) ; push.BW:G src (m16 #2) -(unary-insn-mach 16 push (f-0-4 7) (f-4-3 2) (f-8-4 #x4) push-sem16) +(unary-insn-mach-g 16 push (f-0-4 7) (f-4-3 2) (f-8-4 #x4) push-sem16 $G) ; push.BW:G src (m32 #2) (unary-insn-mach 32 push #xC #x0 #xE push-sem32) @@ -9481,9 +9555,9 @@ ; rot.BW src,dst (dni rot16.b-dst "rot r1h,dest" ((machine 16)) - ("rot.b r1h,${dst16-16-HI}") - (+ (f-0-4 7) (f-4-4 #x4) (f-8-4 #x6) dst16-16-HI) - (rot-2-sem QI dst16-16-HI) + ("rot.b r1h,${dst16-16-QI}") + (+ (f-0-4 7) (f-4-4 #x4) (f-8-4 #x6) dst16-16-QI) + (rot-2-sem QI dst16-16-QI) ()) (dni rot16.w-dst "rot r1h,dest" ((machine 16)) ("rot.w r1h,${dst16-16-HI}") @@ -9492,14 +9566,14 @@ ()) (dni rot32.b-dst "rot r1h,dest" ((machine 32)) - ("rot.b r1h,${dst32-16-Unprefixed-SI}") - (+ (f-0-4 #xA) dst32-16-Unprefixed-SI (f-7-1 0) (f-10-2 3) (f-12-4 #xF)) - (rot-2-sem QI dst32-16-Unprefixed-SI) + ("rot.b r1h,${dst32-16-Unprefixed-QI}") + (+ (f-0-4 #xA) dst32-16-Unprefixed-QI (f-7-1 0) (f-10-2 3) (f-12-4 #xF)) + (rot-2-sem QI dst32-16-Unprefixed-QI) ()) (dni rot32.w-dst "rot r1h,dest" ((machine 32)) - ("rot.w r1h,${dst32-16-Unprefixed-SI}") - (+ (f-0-4 #xA) dst32-16-Unprefixed-SI (f-7-1 1) (f-10-2 3) (f-12-4 #xF)) - (rot-2-sem HI dst32-16-Unprefixed-SI) + ("rot.w r1h,${dst32-16-Unprefixed-HI}") + (+ (f-0-4 #xA) dst32-16-Unprefixed-HI (f-7-1 1) (f-10-2 3) (f-12-4 #xF)) + (rot-2-sem HI dst32-16-Unprefixed-HI) ()) ;------------------------------------------------------------- @@ -9575,7 +9649,7 @@ ) ; sbjnz.size #imm4,dst,label -(arith-jnz-imm4-dst sbjnz (f-0-4 #xF) (f-4-3 4) #xf #x1 sub-jnz-sem) +(arith-jnz-imm4-dst sbjnz s4n (f-0-4 #xF) (f-4-3 4) #xf #x1 sub-jnz-sem) ;------------------------------------------------------------- ; sccnd - store condition on condition (m32) @@ -10105,17 +10179,17 @@ (stzx-sem QI Imm-8-QI Imm-16-QI (reg h-r0l)) ()) (dni stzx16-imm8-imm8-dsp8sb "stzx #Imm8,#Imm8,dsp8[sb]" ((machine 16)) - ("stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[sb]") + ("stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-u8}[sb]") (+ (f-0-4 #xD) (f-4-4 #xD) Imm-8-QI Dsp-16-u8 Imm-24-QI) (stzx-sem QI Imm-8-QI Imm-16-QI (mem16 QI (add (reg h-sb) Dsp-24-u8))) ()) (dni stzx16-imm8-imm8-dsp8fb "stzx #Imm8,#Imm8,dsp8[fb]" ((machine 16)) - ("stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u8[fb]") - (+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-u8 Imm-24-QI) - (stzx-sem QI Imm-8-QI Imm-16-QI (mem16 QI (add (reg h-fb) Dsp-24-u8))) + ("stzx #${Imm-8-QI},#${Imm-24-QI},${Dsp-16-s8}[fb]") + (+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-s8 Imm-24-QI) + (stzx-sem QI Imm-8-QI Imm-24-QI (mem16 QI (add (reg h-fb) Dsp-16-s8))) ()) (dni stzx16-imm8-imm8-abs16 "stzx #Imm8,#Imm8,abs16" ((machine 16)) - ("stzx #${Imm-8-QI},#${Imm-16-QI},Dsp-24-u16") + ("stzx #${Imm-8-QI},#${Imm-32-QI},${Dsp-16-u16}") (+ (f-0-4 #xD) (f-4-4 #xE) Imm-8-QI Dsp-16-u16 Imm-32-QI) (stzx-sem QI Imm-8-QI Imm-32-QI (mem16 QI Dsp-16-u16)) ()) @@ -10149,12 +10223,12 @@ ) ; tst.BW #imm,dst (m16 #1 m32 #1) -(binary-arith-imm-dst tst X (f-0-4 7) (f-4-3 3) (f-8-4 0) #x9 #x3 #xE tst-sem) +(binary-arith-imm-dst tst G (f-0-4 7) (f-4-3 3) (f-8-4 0) #x9 #x3 #xE tst-sem) ; tst.BW src,dst (m16 #2 m32 #3) (binary-arith16-src-dst-defn QI QI .b 0 tst X (f-0-4 #x8) (f-4-3 0) tst-sem) (binary-arith16-src-dst-defn HI HI .w 1 tst X (f-0-4 #x8) (f-4-3 0) tst-sem) -(binary-arith32-src-dst-Prefixed QI QI .b 0 tst X #x1 #x9 tst-sem) -(binary-arith32-src-dst-Prefixed HI HI .w 1 tst X #x1 #x9 tst-sem) +(binary-arith32-src-dst-Prefixed QI QI .b 0 tst G #x1 #x9 tst-sem) +(binary-arith32-src-dst-Prefixed HI HI .w 1 tst G #x1 #x9 tst-sem) ; tst.BW:S #imm,dst2 (m32 #2) (binary-arith32-s-imm-dst QI .b 0 tst #x0 #x6 tst-sem) (binary-arith32-s-imm-dst HI .w 1 tst #x0 #x6 tst-sem) @@ -10215,7 +10289,7 @@ (xchg16-defn QI b 0 1 r0h) (xchg16-defn QI b 0 2 r1l) (xchg16-defn QI b 0 3 r1h) -(xchg16-defn QI w 1 0 r0) +(xchg16-defn HI w 1 0 r0) (xchg16-defn HI w 1 1 r1) (xchg16-defn HI w 1 2 r2) (xchg16-defn HI w 1 3 r3) diff --git a/cpu/m32c.opc b/cpu/m32c.opc index 19547ae..6235326 100644 --- a/cpu/m32c.opc +++ b/cpu/m32c.opc @@ -69,6 +69,10 @@ m32c_asm_hash (const char *mnem) if (mnem[0] == 's' && mnem[1] == 'c') return 's'; + /* Don't hash bmCND */ + if (mnem[0] == 'b' && mnem[1] == 'm') + return 'b'; + for (h = 0; *mnem && *mnem != ' ' && *mnem != ':'; ++mnem) h += *mnem; return h % CGEN_ASM_HASH_SIZE; @@ -218,6 +222,31 @@ parse_signed4 (CGEN_CPU_DESC cd, const char **strp, } static const char * +parse_signed4n (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value; + long have_zero = 0; + + if (strncmp (*strp, "0x0", 3) == 0 + || (**strp == '0' && *(*strp + 1) != 'x')) + have_zero = 1; + + PARSE_SIGNED; + + if (value < -7 || value > 8) + return _("Immediate is out of range -7 to 8"); + + /* If this field may require a relocation then use larger dsp16. */ + if (! have_zero && value == 0) + return _("Immediate is out of range -7 to 8"); + + *valuep = -value; + return 0; +} + +static const char * parse_signed8 (CGEN_CPU_DESC cd, const char **strp, int opindex, signed long *valuep) { @@ -433,6 +462,26 @@ parse_unsigned24 (CGEN_CPU_DESC cd, const char **strp, return 0; } +/* This should only be used for #imm->reg. */ +static const char * +parse_signed24 (CGEN_CPU_DESC cd, const char **strp, + int opindex, signed long *valuep) +{ + const char *errmsg = 0; + signed long value; + + PARSE_SIGNED; + + if (value <= 0xffffff && value > 0x7fffff) + value -= 0x1000000; + + if (value > 0xffffff) + return _("dsp:24 immediate is out of range"); + + *valuep = value; + return 0; +} + static const char * parse_signed32 (CGEN_CPU_DESC cd, const char **strp, int opindex, signed long *valuep) @@ -775,14 +824,14 @@ m32c_cgen_insn_supported (CGEN_CPU_DESC cd, const CGEN_INSN *insn) { int machs = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_MACH); - int isas = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_ISA); + CGEN_BITSET isas = CGEN_INSN_BITSET_ATTR_VALUE (insn, CGEN_INSN_ISA); /* If attributes are absent, assume no restriction. */ if (machs == 0) machs = ~0; return ((machs & cd->machs) - && (isas & cd->isas)); + && cgen_bitset_intersect_p (& isas, cd->isas)); } /* Parse a set of registers, R0,R1,A0,A1,SB,FB. */ @@ -1072,3 +1121,16 @@ print_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, { print_regset (cd, dis_info, value, attrs, pc, length, PUSH); } + +static void +print_signed4n (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void * dis_info, + signed long value, + unsigned int attrs ATTRIBUTE_UNUSED, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) +{ + disassemble_info *info = dis_info; + + (*info->fprintf_func) (info->stream, "%ld", -value); +} diff --git a/cpu/m32r.opc b/cpu/m32r.opc index f2351b1..ab69d07 100644 --- a/cpu/m32r.opc +++ b/cpu/m32r.opc @@ -127,7 +127,10 @@ parse_hi16 (CGEN_CPU_DESC cd, ++*strp; if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) - value >>= 16; + { + value >>= 16; + value &= 0xffff; + } *valuep = value; return errmsg; } @@ -142,8 +145,9 @@ parse_hi16 (CGEN_CPU_DESC cd, if (errmsg == NULL && result_type == CGEN_PARSE_OPERAND_RESULT_NUMBER) { - value = value + (value & 0x8000 ? 0x10000 : 0); + value += 0x8000; value >>= 16; + value &= 0xffff; } *valuep = value; return errmsg; |