cpu,gas,opcodes: support for eBPF JMP32 instruction class

Add support for the JMP32 class of eBPF instructions.

cpu/ChangeLog

	* bpf.cpu (define-cond-jump-insn): Renamed from djci.
	(dcji) New version with support for JMP32

gas/ChangeLog

	* testsuite/gas/bpf/bpf.exp: Run jump32 tests.
	* testsuite/gas/bpf/jump32.s: New file.
	* testsuite/gas/bpf/jump32.d: Likewise.

opcodes/ChangeLog

	* bpf-desc.c: Regenerate.
	* bpf-desc.h: Likewise.
	* bpf-opc.c: Regenerate.
	* bpf-opc.h: Likewise.

2 files changed, 22 insertions, 12 deletions

diff --git a/cpu/ChangeLog b/cpu/ChangeLog
index f67c869..2324006 100644
--- a/cpu/ChangeLog
+++ b/cpu/ChangeLog
@@ -1,3 +1,8 @@
+2020-02-16  David Faust  <david.faust@oracle.com>
+
+	* bpf.cpu (define-cond-jump-insn): Renamed from djci.
+	(dcji) New version with support for JMP32
+
 2020-02-03  Alan Modra  <amodra@gmail.com>
 
 	* m32c.cpu (f-dsp-64-s16): Mask before shifting signed value.
diff --git a/cpu/bpf.cpu b/cpu/bpf.cpu
index 1378bda..89a27fe 100644
--- a/cpu/bpf.cpu
+++ b/cpu/bpf.cpu
@@ -222,7 +222,7 @@
 (define-normal-insn-enum insn-op-class "eBPF instruction class"
   (all-isas) OP_CLASS_ f-op-class
   ((LD    #b000) (LDX   #b001) (ST    #b010) (STX   #b011)
-   (ALU   #b100) (JMP   #b101) (ALU64 #b111)))
+   (ALU   #b100) (JMP   #b101) (JMP32 #b110) (ALU64 #b111)))
 
 ;; For load/store instructions, the 8-bit code field is subdivided in:
 ;;
@@ -583,25 +583,30 @@
 ;; registers.  Therefore, we need to define several variants in both
 ;; ISAs:
 ;;
-;;   J{eq,gt,ge,lt,le,set,ne,sgt,sge,slt,sle}{i,r}le for the
+;;   J{eq,gt,ge,lt,le,set,ne,sgt,sge,slt,sle}[32]{i,r}le for the
 ;;   little-endian ISA.
-;;   J{eq,gt,ge,lt,le,set,ne.sgt,sge,slt,sle}{i,r}be for the
+;;   J{eq,gt,ge,lt,le,set,ne.sgt,sge,slt,sle}[32]{i,r}be for the
 ;;   big-endian ISA.
 
-(define-pmacro (dcji x-cond x-op-code x-endian)
+(define-pmacro (define-cond-jump-insn x-cond x-suffix x-op-class x-op-code x-endian)
   (begin
-    (dni (.sym j x-cond i x-endian)
-         (.str j x-cond "i")
+    (dni (.sym j x-cond x-suffix i x-endian)
+         (.str j x-cond x-suffix " i")
          ((ISA (.sym ebpf x-endian)))
-         (.str "j" x-cond " $dst" x-endian ",$imm32,$disp16")
+         (.str "j" x-cond x-suffix " $dst" x-endian ",$imm32,$disp16")
          (+ imm32 disp16 ((.sym f-src x-endian) 0) (.sym dst x-endian)
-            OP_CLASS_JMP OP_SRC_K (.sym OP_CODE_ x-op-code)) () ())
-    (dni (.sym j x-cond r x-endian)
-         (.str j x-cond "r")
+            x-op-class OP_SRC_K (.sym OP_CODE_ x-op-code)) () ())
+    (dni (.sym j x-cond x-suffix r x-endian)
+         (.str j x-cond x-suffix " r")
          ((ISA (.sym ebpf x-endian)))
-         (.str "j" x-cond " $dst" x-endian ",$src" x-endian ",$disp16")
+         (.str "j" x-cond x-suffix " $dst" x-endian ",$src" x-endian ",$disp16")
          (+ (f-imm32 0) disp16 (.sym src x-endian) (.sym dst x-endian)
-            OP_CLASS_JMP OP_SRC_X (.sym OP_CODE_ x-op-code)) () ())))
+            x-op-class OP_SRC_X (.sym OP_CODE_ x-op-code)) () ())))
+
+(define-pmacro (dcji x-cond x-op-code x-endian)
+  (begin
+    (define-cond-jump-insn x-cond "" OP_CLASS_JMP x-op-code x-endian)
+    (define-cond-jump-insn x-cond "32" OP_CLASS_JMP32 x-op-code x-endian)))
 
 (define-pmacro (define-condjump-insns x-endian)
   (begin