Remove support for the (deprecated) openrisc and or32 configurations and replace

with support for the new or1k configuration.

1 files changed, 222 insertions, 0 deletions

diff --git a/cpu/or1korfpx.cpu b/cpu/or1korfpx.cpu
new file mode 100644
index 0000000..1a128a9
--- /dev/null
+++ b/cpu/or1korfpx.cpu
@@ -0,0 +1,222 @@
+; OpenRISC 1000 architecture.  -*- Scheme -*-
+; Copyright 2000-2014 Free Software Foundation, Inc.
+; Contributed by Peter Gavin, pgavin@gmail.com
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, see <http://www.gnu.org/licenses/>
+
+; Initial ORFPX32 instruction set
+
+; I'm not sure how CGEN handles rounding in FP operations, except for
+; in conversions to/from integers.  So lf.add, lf.sub, lf.mul, and
+; lf.div do not round according to the FPCSR RM field.
+; NaN, overflow, and underflow are not yet handled either.
+
+(define-normal-insn-enum insn-opcode-float-regreg
+  "floating point reg/reg insn opcode enums" ()
+  OPC_FLOAT_REGREG_ f-op-7-8
+  (("ADD_S"  #x00)
+   ("SUB_S"  #x01)
+   ("MUL_S"  #x02)
+   ("DIV_S"  #x03)
+   ("ITOF_S" #x04)
+   ("FTOI_S" #x05)
+   ("REM_S"  #x06)
+   ("MADD_S" #x07)
+   ("SFEQ_S" #x08)
+   ("SFNE_S" #x09)
+   ("SFGT_S" #x0a)
+   ("SFGE_S" #x0b)
+   ("SFLT_S" #x0c)
+   ("SFLE_S" #x0d)
+   ("ADD_D"  #x10)
+   ("SUB_D"  #x11)
+   ("MUL_D"  #x12)
+   ("DIV_D"  #x13)
+   ("ITOF_D" #x14)
+   ("FTOI_D" #x15)
+   ("REM_D"  #x16)
+   ("MADD_D" #x17)
+   ("SFEQ_D" #x18)
+   ("SFNE_D" #x19)
+   ("SFGT_D" #x1a)
+   ("SFGE_D" #x1b)
+   ("SFLT_D" #x1c)
+   ("SFLE_D" #x1d)
+   ("CUST1_S" #xd0)
+   ("CUST1_D" #xe0)
+   )
+  )
+
+(dnop rDSF "destination register (single floating point mode)" () h-fsr f-r1)
+(dnop rASF "source register A (single floating point mode)"    () h-fsr f-r2)
+(dnop rBSF "source register B (single floating point mode)"    () h-fsr f-r3)
+
+(dnop rDDF "destination register (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
+(dnop rADF "source register A (double floating point mode)"    ((MACH ORFPX64-MACHS)) h-fdr f-r1)
+(dnop rBDF "source register B (double floating point mode)"    ((MACH ORFPX64-MACHS)) h-fdr f-r1)
+
+(define-pmacro (float-regreg-insn mnemonic)
+  (begin
+    (dni (.sym lf- mnemonic -s)
+         (.str "lf." mnemonic ".s reg/reg/reg")
+         ((MACH ORFPX-MACHS))
+         (.str "lf." mnemonic ".s $rDSF,$rASF,$rBSF")
+         (+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _S))
+         (set SF rDSF (mnemonic SF rASF rBSF))
+         ()
+         )
+    (dni (.sym lf- mnemonic -d)
+         (.str "lf." mnemonic ".d reg/reg/reg")
+         ((MACH ORFPX64-MACHS))
+         (.str "lf." mnemonic ".d $rDDF,$rADF,$rBDF")
+         (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _D))
+         (set DF rDDF (mnemonic DF rADF rBDF))
+         ()
+         )
+    )
+  )
+
+(float-regreg-insn add)
+(float-regreg-insn sub)
+(float-regreg-insn mul)
+(float-regreg-insn div)
+
+(dni lf-rem-s
+     "lf.rem.s reg/reg/reg"
+     ((MACH ORFPX-MACHS))
+     "lf.rem.s $rDSF,$rASF,$rBSF"
+     (+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_S)
+     (set SF rDSF (rem SF rASF rBSF))
+     ()
+     )
+(dni lf-rem-d
+     "lf.rem.d reg/reg/reg"
+     ((MACH ORFPX64-MACHS))
+     "lf.rem.d $rDDF,$rADF,$rBDF"
+     (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_D)
+     (set DF rDDF (mod DF rADF rBDF))
+     ()
+     )
+
+(define-pmacro (get-rounding-mode)
+  (case INT sys-fpcsr-rm
+        ((0) 1) ; TIES-TO-EVEN -- I'm assuming this is what is meant by "round to nearest"
+        ((1) 3) ; TOWARD-ZERO
+        ((2) 4) ; TOWARD-POSITIVE
+        (else 5) ; TOWARD-NEGATIVE
+        )
+  )
+
+(dni lf-itof-s
+     "lf.itof.s reg/reg"
+     ((MACH ORFPX-MACHS))
+     "lf.itof.s $rDSF,$rA"
+     (+ OPC_FLOAT rDSF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_S)
+     (set SF rDSF (float SF (get-rounding-mode) (trunc SI rA)))
+     ()
+     )
+(dni lf-itof-d
+     "lf.itof.d reg/reg"
+     ((MACH ORFPX64-MACHS))
+     "lf.itof.d $rDSF,$rA"
+     (+ OPC_FLOAT rDSF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_D)
+     (set DF rDDF (float DF (get-rounding-mode) rA))
+     ()
+     )
+
+(dni lf-ftoi-s
+     "lf.ftoi.s reg/reg"
+     ((MACH ORFPX-MACHS))
+     "lf.ftoi.s $rD,$rASF"
+     (+ OPC_FLOAT rD rASF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_S)
+     (set WI rD (ext WI (fix SI (get-rounding-mode) rASF)))
+     ()
+     )
+
+(dni lf-ftoi-d
+     "lf.ftoi.d reg/reg"
+     ((MACH ORFPX64-MACHS))
+     "lf.ftoi.d $rD,$rADF"
+     (+ OPC_FLOAT rD rADF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_D)
+     (set DI rD (fix DI (get-rounding-mode) rADF))
+     ()
+     )
+
+(define-pmacro (float-setflag-insn mnemonic)
+  (begin
+    (dni (.sym lf- mnemonic -s)
+         (.str "lf.sf" mnemonic ".s reg/reg")
+         ((MACH ORFPX-MACHS))
+         (.str "lf.sf" mnemonic ".s $rASF,$rBSF")
+         (+ OPC_FLOAT (f-r1 0) rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _S))
+         (set BI sys-sr-f (mnemonic SF rASF rBSF))
+         ()
+         )
+    (dni (.sym lf- mnemonic -d)
+         (.str "lf.sf" mnemonic ".d reg/reg")
+         ((MACH ORFPX64-MACHS))
+         (.str "lf.sf" mnemonic ".d $rASF,$rBSF")
+         (+ OPC_FLOAT (f-r1 0) rASF rBSF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D))
+         (set BI sys-sr-f (mnemonic DF rADF rBDF))
+         ()
+         )
+    )
+  )
+
+(float-setflag-insn eq)
+(float-setflag-insn ne)
+(float-setflag-insn ge)
+(float-setflag-insn gt)
+(float-setflag-insn lt)
+(float-setflag-insn le)
+
+(dni lf-madd-s
+     "lf.madd.s reg/reg/reg"
+     ((MACH ORFPX-MACHS))
+     "lf.madd.s $rDSF,$rASF,$rBSF"
+     (+ OPC_FLOAT rDSF rASF rBSF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_S)
+     (set SF rDSF (add SF (mul SF rASF rBSF) rDSF))
+     ()
+     )
+(dni lf-madd-d
+     "lf.madd.d reg/reg/reg"
+     ((MACH ORFPX64-MACHS))
+     "lf.madd.d $rDDF,$rADF,$rBDF"
+     (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_D)
+     (set DF rDDF (add DF (mul DF rADF rBDF) rDDF))
+     ()
+     )
+
+(define-pmacro (float-cust-insn cust-num)
+  (begin
+    (dni (.sym "lf-cust" cust-num "-s")
+         (.str "lf.cust" cust-num ".s")
+         ((MACH ORFPX-MACHS))
+         (.str "lf.cust" cust-num ".s $rASF,$rBSF")
+         (+ OPC_FLOAT (f-resv-25-5 0) rASF rBSF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_S"))
+         (nop)
+         ()
+         )
+    (dni (.sym "lf-cust" cust-num "-d")
+         (.str "lf.cust" cust-num ".d")
+         ((MACH ORFPX64-MACHS))
+         (.str "lf.cust" cust-num ".d")
+         (+ OPC_FLOAT (f-resv-25-5 0) rADF rBDF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_D"))
+         (nop)
+         ()
+         )
+    )
+  )
+
+(float-cust-insn "1")