MIPS16: Handle non-extensible instructions correctly

Identify non-extensible instructions in the MIPS16 opcode table and
disallow their use with the `.e' instruction size suffix in assembly and
do not interpret any EXTEND prefix present as a part of the instruction
in disassembly.

According to all versions of the MIPS16 ASE specifications the following
instructions encodings are not extensible [1][2][3][4][5][6]: I8/MOV32R,
I8/MOVR32, all RRR minor opcodes, all RR minor opcodes except from DSRA
and DSRL, and EXTEND itself, and as from revision 2.50 of the MIPS16e
ASE specifications it has been further clarified what was previously
implied, that non-extesiable instructions when preceded with an EXTEND
prefix must cause a Reserved Instruction exception [3][5].

Therefore in the presence of an EXTEND prefix none of these instructions
are supposed to be handled as extended instructions and supporting these
forms in disassembly causes confusion, and in the case of the RRR major
opcode it also clashes with the ASMACRO encoding.

References:

[1] "Product Description, MIPS16 Application-Specific Extension",
    Version 1.3, MIPS Technologies, Inc., 970130, Table 3. "MIPS16
    Instruction Set Summary", p. 5

[2] same, Table 5 "RR Minor Opcodes (RR-type instructions)", p.10

[3] "MIPS32 Architecture for Programmers, Volume IV-a: The MIPS16e
    Application-Specific Extension to the MIPS32 Architecture", MIPS
    Technologies, Inc., Document Number: MD00076, Revision 2.63, July
    16, 2013, Section 3.9 "MIPS16e Instruction Summaries", pp. 37-39

[4] same, Section 3.15 "Instruction Bit Encoding", pp. 46-49

[5] "MIPS64 Architecture for Programmers, Volume IV-a: The MIPS16e
    Application-Specific Extension to the MIPS64 Architecture", MIPS
    Technologies, Inc., Document Number: MD00077, Revision 2.60, June
    25, 2008, Section 1.9 "MIPS16e Instruction Summaries", pp. 38-41

[6] same, Section 1.15 "Instruction Bit Encoding", pp. 48-51

	include/
	* opcode/mips.h (INSN2_SHORT_ONLY): New macro.

	gas/
	* config/tc-mips.c (is_size_valid_16): Disallow a `.e' suffix
	instruction size override for INSN2_SHORT_ONLY opcode table
	entries.
	* testsuite/gas/mips/mips16-extend-swap.d: Adjust output.
	* testsuite/gas/mips/mips16-macro-e.l: Adjust error messages.
	* testsuite/gas/mips/mips16-32@mips16-macro-e.l: Adjust error
	messages.
	* testsuite/gas/mips/mips16e-32@mips16-macro-e.l: Adjust error
	messages.
	* testsuite/gas/mips/mips16-insn-e.d: New test.
	* testsuite/gas/mips/mips16-insn-t.d: New test.
	* testsuite/gas/mips/mips16-32@mips16-insn-e.d: New test.
	* testsuite/gas/mips/mips16-64@mips16-insn-e.d: New test.
	* testsuite/gas/mips/mips16e-32@mips16-insn-e.d: New test.
	* testsuite/gas/mips/mips16-32@mips16-insn-t.d: New test.
	* testsuite/gas/mips/mips16-64@mips16-insn-t.d: New test.
	* testsuite/gas/mips/mips16e-32@mips16-insn-t.d: New test.
	* testsuite/gas/mips/mips16-insn-e.l: New stderr output.
	* testsuite/gas/mips/mips16-insn-t.l: New stderr output.
	* testsuite/gas/mips/mips16-32@mips16-insn-e.l: New stderr
	output.
	* testsuite/gas/mips/mips16-64@mips16-insn-e.l: New stderr
	output.
	* testsuite/gas/mips/mips16e-32@mips16-insn-e.l: New stderr
	output.
	* testsuite/gas/mips/mips16-32@mips16-insn-t.l: New stderr
	output.
	* testsuite/gas/mips/mips16-64@mips16-insn-t.l: New stderr
	output.
	* testsuite/gas/mips/mips16e-32@mips16-insn-t.l: New stderr
	output.
	* testsuite/gas/mips/mips16-insn-e.s: New test source.
	* testsuite/gas/mips/mips16-insn-t.s: New test source.
	* testsuite/gas/mips/mips.exp: Run the new tests.

	opcodes/
	* mips-dis.c (print_insn_mips16): Disallow EXTEND prefix
	matching for INSN2_SHORT_ONLY opcode table entries.
	* mips16-opc.c (SH): New macro.
	(mips16_opcodes): Set SH in `pinfo2' for non-extensible
	instruction entries: "nop", "addu", "and", "break", "cmp",
	"daddu", "ddiv", "ddivu", "div", "divu", "dmult", "dmultu",
	"drem", "dremu", "dsllv", "dsll", "dsrav", "dsra", "dsrlv",
	"dsrl", "dsubu", "exit", "entry", "jalr", "jal", "jr", "j",
	"jalrc", "jrc", "mfhi", "mflo", "move", "mult", "multu", "neg",
	"not", "or", "rem", "remu", "sllv", "sll", "slt", "sltu",
	"srav", "sra", "srlv", "srl", "subu", "xor", "sdbbp", "seb",
	"seh", "sew", "zeb", "zeh", "zew" and "extend".

	binutils/
	* testsuite/binutils-all/mips/mips16-extend-insn.d: New test.
	* testsuite/binutils-all/mips/mips16-extend-insn.s: New test
	source.
	* testsuite/binutils-all/mips/mips.exp: Run the new tests.

4 files changed, 973 insertions, 0 deletions

diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 3e45f64..f378262 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,10 @@
+2016-12-23  Maciej W. Rozycki  <macro@imgtec.com>
+
+	* testsuite/binutils-all/mips/mips16-extend-insn.d: New test.
+	* testsuite/binutils-all/mips/mips16-extend-insn.s: New test
+	source.
+	* testsuite/binutils-all/mips/mips.exp: Run the new tests.
+
 2016-12-23  Tristan Gingold  <gingold@adacore.com>
 
 	* configure: Regenerate.
diff --git a/binutils/testsuite/binutils-all/mips/mips.exp b/binutils/testsuite/binutils-all/mips/mips.exp
index 143fbc4..8393fc0 100644
--- a/binutils/testsuite/binutils-all/mips/mips.exp
+++ b/binutils/testsuite/binutils-all/mips/mips.exp
@@ -29,4 +29,5 @@ if [is_elf_format] {
     run_dump_test "mips16-undecoded"
     run_dump_test "mips16-pcrel"
     run_dump_test "mips16-extend-noinsn"
+    run_dump_test "mips16-extend-insn"
 }
diff --git a/binutils/testsuite/binutils-all/mips/mips16-extend-insn.d b/binutils/testsuite/binutils-all/mips/mips16-extend-insn.d
new file mode 100644
index 0000000..fc170c6
--- /dev/null
+++ b/binutils/testsuite/binutils-all/mips/mips16-extend-insn.d
@@ -0,0 +1,335 @@
+#PROG: objcopy
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS16 extensible and non-extensible instruction disassembly
+#as: -32 -mips64
+
+# Verify interpreted and separate respectively EXTEND prefix disassembly
+# for extensible and non-extensible instructions.
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> f123 0000 	addiu	s0,sp,6432
+[0-9a-f]+ <[^>]*> f123 0020 	addiu	s0,sp,6432
+[0-9a-f]+ <[^>]*> f123 0040 	addiu	s0,sp,6432
+[0-9a-f]+ <[^>]*> f123 0060 	addiu	s0,sp,6432
+[0-9a-f]+ <[^>]*> f123 0080 	addiu	s0,sp,6432
+[0-9a-f]+ <[^>]*> f123 00a0 	addiu	s0,sp,6432
+[0-9a-f]+ <[^>]*> f123 00c0 	addiu	s0,sp,6432
+[0-9a-f]+ <[^>]*> f123 00e0 	addiu	s0,sp,6432
+[0-9a-f]+ <[^>]*> f123 0800 	la	s0,00001940 <foo\+0x1940>
+[0-9a-f]+ <[^>]*> f123 0820 	la	s0,00001944 <foo\+0x1944>
+[0-9a-f]+ <[^>]*> f123 0840 	la	s0,00001948 <foo\+0x1948>
+[0-9a-f]+ <[^>]*> f123 0860 	la	s0,0000194c <foo\+0x194c>
+[0-9a-f]+ <[^>]*> f123 0880 	la	s0,00001950 <foo\+0x1950>
+[0-9a-f]+ <[^>]*> f123 08a0 	la	s0,00001954 <foo\+0x1954>
+[0-9a-f]+ <[^>]*> f123 08c0 	la	s0,00001958 <foo\+0x1958>
+[0-9a-f]+ <[^>]*> f123 08e0 	la	s0,0000195c <foo\+0x195c>
+[0-9a-f]+ <[^>]*> f123 1000 	b	00003284 <foo\+0x3284>
+[0-9a-f]+ <[^>]*> f123 1020 	b	00003288 <foo\+0x3288>
+[0-9a-f]+ <[^>]*> f123 1040 	b	0000328c <foo\+0x328c>
+[0-9a-f]+ <[^>]*> f123 1060 	b	00003290 <foo\+0x3290>
+[0-9a-f]+ <[^>]*> f123 1080 	b	00003294 <foo\+0x3294>
+[0-9a-f]+ <[^>]*> f123 10a0 	b	00003298 <foo\+0x3298>
+[0-9a-f]+ <[^>]*> f123 10c0 	b	0000329c <foo\+0x329c>
+[0-9a-f]+ <[^>]*> f123 10e0 	b	000032a0 <foo\+0x32a0>
+[0-9a-f]+ <[^>]*> f123 2000 	beqz	s0,000032a4 <foo\+0x32a4>
+[0-9a-f]+ <[^>]*> f123 2020 	beqz	s0,000032a8 <foo\+0x32a8>
+[0-9a-f]+ <[^>]*> f123 2040 	beqz	s0,000032ac <foo\+0x32ac>
+[0-9a-f]+ <[^>]*> f123 2060 	beqz	s0,000032b0 <foo\+0x32b0>
+[0-9a-f]+ <[^>]*> f123 2080 	beqz	s0,000032b4 <foo\+0x32b4>
+[0-9a-f]+ <[^>]*> f123 20a0 	beqz	s0,000032b8 <foo\+0x32b8>
+[0-9a-f]+ <[^>]*> f123 20c0 	beqz	s0,000032bc <foo\+0x32bc>
+[0-9a-f]+ <[^>]*> f123 20e0 	beqz	s0,000032c0 <foo\+0x32c0>
+[0-9a-f]+ <[^>]*> f123 2800 	bnez	s0,000032c4 <foo\+0x32c4>
+[0-9a-f]+ <[^>]*> f123 2820 	bnez	s0,000032c8 <foo\+0x32c8>
+[0-9a-f]+ <[^>]*> f123 2840 	bnez	s0,000032cc <foo\+0x32cc>
+[0-9a-f]+ <[^>]*> f123 2860 	bnez	s0,000032d0 <foo\+0x32d0>
+[0-9a-f]+ <[^>]*> f123 2880 	bnez	s0,000032d4 <foo\+0x32d4>
+[0-9a-f]+ <[^>]*> f123 28a0 	bnez	s0,000032d8 <foo\+0x32d8>
+[0-9a-f]+ <[^>]*> f123 28c0 	bnez	s0,000032dc <foo\+0x32dc>
+[0-9a-f]+ <[^>]*> f123 28e0 	bnez	s0,000032e0 <foo\+0x32e0>
+[0-9a-f]+ <[^>]*> f123 3000 	sll	s0,4
+[0-9a-f]+ <[^>]*> f123 3004 	sll	s0,4
+[0-9a-f]+ <[^>]*> f123 3008 	sll	s0,4
+[0-9a-f]+ <[^>]*> f123 300c 	sll	s0,4
+[0-9a-f]+ <[^>]*> f123 3010 	sll	s0,4
+[0-9a-f]+ <[^>]*> f123 3014 	sll	s0,4
+[0-9a-f]+ <[^>]*> f123 3018 	sll	s0,4
+[0-9a-f]+ <[^>]*> f123 301c 	sll	s0,4
+[0-9a-f]+ <[^>]*> f123 3001 	dsll	s0,36
+[0-9a-f]+ <[^>]*> f123 3005 	dsll	s0,36
+[0-9a-f]+ <[^>]*> f123 3009 	dsll	s0,36
+[0-9a-f]+ <[^>]*> f123 300d 	dsll	s0,36
+[0-9a-f]+ <[^>]*> f123 3011 	dsll	s0,36
+[0-9a-f]+ <[^>]*> f123 3015 	dsll	s0,36
+[0-9a-f]+ <[^>]*> f123 3019 	dsll	s0,36
+[0-9a-f]+ <[^>]*> f123 301d 	dsll	s0,36
+[0-9a-f]+ <[^>]*> f123 3002 	srl	s0,4
+[0-9a-f]+ <[^>]*> f123 3006 	srl	s0,4
+[0-9a-f]+ <[^>]*> f123 300a 	srl	s0,4
+[0-9a-f]+ <[^>]*> f123 300e 	srl	s0,4
+[0-9a-f]+ <[^>]*> f123 3012 	srl	s0,4
+[0-9a-f]+ <[^>]*> f123 3016 	srl	s0,4
+[0-9a-f]+ <[^>]*> f123 301a 	srl	s0,4
+[0-9a-f]+ <[^>]*> f123 301e 	srl	s0,4
+[0-9a-f]+ <[^>]*> f123 3003 	sra	s0,4
+[0-9a-f]+ <[^>]*> f123 3007 	sra	s0,4
+[0-9a-f]+ <[^>]*> f123 300b 	sra	s0,4
+[0-9a-f]+ <[^>]*> f123 300f 	sra	s0,4
+[0-9a-f]+ <[^>]*> f123 3013 	sra	s0,4
+[0-9a-f]+ <[^>]*> f123 3017 	sra	s0,4
+[0-9a-f]+ <[^>]*> f123 301b 	sra	s0,4
+[0-9a-f]+ <[^>]*> f123 301f 	sra	s0,4
+[0-9a-f]+ <[^>]*> f123 3800 	ld	s0,6432\(s0\)
+[0-9a-f]+ <[^>]*> f123 4000 	addiu	s0,s0,6432
+[0-9a-f]+ <[^>]*> f123 4010 	daddiu	s0,s0,6432
+[0-9a-f]+ <[^>]*> f123 4800 	addiu	s0,6432
+[0-9a-f]+ <[^>]*> f123 4820 	addiu	s0,6432
+[0-9a-f]+ <[^>]*> f123 4840 	addiu	s0,6432
+[0-9a-f]+ <[^>]*> f123 4860 	addiu	s0,6432
+[0-9a-f]+ <[^>]*> f123 4880 	addiu	s0,6432
+[0-9a-f]+ <[^>]*> f123 48a0 	addiu	s0,6432
+[0-9a-f]+ <[^>]*> f123 48c0 	addiu	s0,6432
+[0-9a-f]+ <[^>]*> f123 48e0 	addiu	s0,6432
+[0-9a-f]+ <[^>]*> f123 5000 	slti	s0,6432
+[0-9a-f]+ <[^>]*> f123 5020 	slti	s0,6432
+[0-9a-f]+ <[^>]*> f123 5040 	slti	s0,6432
+[0-9a-f]+ <[^>]*> f123 5060 	slti	s0,6432
+[0-9a-f]+ <[^>]*> f123 5080 	slti	s0,6432
+[0-9a-f]+ <[^>]*> f123 50a0 	slti	s0,6432
+[0-9a-f]+ <[^>]*> f123 50c0 	slti	s0,6432
+[0-9a-f]+ <[^>]*> f123 50e0 	slti	s0,6432
+[0-9a-f]+ <[^>]*> f123 5800 	sltiu	s0,6432
+[0-9a-f]+ <[^>]*> f123 5820 	sltiu	s0,6432
+[0-9a-f]+ <[^>]*> f123 5840 	sltiu	s0,6432
+[0-9a-f]+ <[^>]*> f123 5860 	sltiu	s0,6432
+[0-9a-f]+ <[^>]*> f123 5880 	sltiu	s0,6432
+[0-9a-f]+ <[^>]*> f123 58a0 	sltiu	s0,6432
+[0-9a-f]+ <[^>]*> f123 58c0 	sltiu	s0,6432
+[0-9a-f]+ <[^>]*> f123 58e0 	sltiu	s0,6432
+[0-9a-f]+ <[^>]*> f123 6000 	bteqz	000033d0 <foo\+0x33d0>
+[0-9a-f]+ <[^>]*> f123 6020 	bteqz	000033d4 <foo\+0x33d4>
+[0-9a-f]+ <[^>]*> f123 6040 	bteqz	000033d8 <foo\+0x33d8>
+[0-9a-f]+ <[^>]*> f123 6060 	bteqz	000033dc <foo\+0x33dc>
+[0-9a-f]+ <[^>]*> f123 6080 	bteqz	000033e0 <foo\+0x33e0>
+[0-9a-f]+ <[^>]*> f123 60a0 	bteqz	000033e4 <foo\+0x33e4>
+[0-9a-f]+ <[^>]*> f123 60c0 	bteqz	000033e8 <foo\+0x33e8>
+[0-9a-f]+ <[^>]*> f123 60e0 	bteqz	000033ec <foo\+0x33ec>
+[0-9a-f]+ <[^>]*> f123 6100 	btnez	000033f0 <foo\+0x33f0>
+[0-9a-f]+ <[^>]*> f123 6120 	btnez	000033f4 <foo\+0x33f4>
+[0-9a-f]+ <[^>]*> f123 6140 	btnez	000033f8 <foo\+0x33f8>
+[0-9a-f]+ <[^>]*> f123 6160 	btnez	000033fc <foo\+0x33fc>
+[0-9a-f]+ <[^>]*> f123 6180 	btnez	00003400 <foo\+0x3400>
+[0-9a-f]+ <[^>]*> f123 61a0 	btnez	00003404 <foo\+0x3404>
+[0-9a-f]+ <[^>]*> f123 61c0 	btnez	00003408 <foo\+0x3408>
+[0-9a-f]+ <[^>]*> f123 61e0 	btnez	0000340c <foo\+0x340c>
+[0-9a-f]+ <[^>]*> f123 6200 	sw	ra,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 6220 	sw	ra,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 6240 	sw	ra,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 6280 	sw	ra,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 62a0 	sw	ra,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 62c0 	sw	ra,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 62e0 	sw	ra,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 6200 	sw	ra,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 6300 	addiu	sp,6432
+[0-9a-f]+ <[^>]*> f123 6320 	addiu	sp,6432
+[0-9a-f]+ <[^>]*> f123 6340 	addiu	sp,6432
+[0-9a-f]+ <[^>]*> f123 6360 	addiu	sp,6432
+[0-9a-f]+ <[^>]*> f123 6380 	addiu	sp,6432
+[0-9a-f]+ <[^>]*> f123 63a0 	addiu	sp,6432
+[0-9a-f]+ <[^>]*> f123 63c0 	addiu	sp,6432
+[0-9a-f]+ <[^>]*> f123 63e0 	addiu	sp,6432
+[0-9a-f]+ <[^>]*> f123 6400 	restore	256,s2,a1-a3
+[0-9a-f]+ <[^>]*> f123 6480 	save	256,s2,a1-a3
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> 6500      	nop
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> 6501      	move	zero,s1
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> 6700      	move	s0,zero
+[0-9a-f]+ <[^>]*> f123 6800 	li	s0,6432
+[0-9a-f]+ <[^>]*> f123 6820 	li	s0,6432
+[0-9a-f]+ <[^>]*> f123 6840 	li	s0,6432
+[0-9a-f]+ <[^>]*> f123 6860 	li	s0,6432
+[0-9a-f]+ <[^>]*> f123 6880 	li	s0,6432
+[0-9a-f]+ <[^>]*> f123 68a0 	li	s0,6432
+[0-9a-f]+ <[^>]*> f123 68c0 	li	s0,6432
+[0-9a-f]+ <[^>]*> f123 68e0 	li	s0,6432
+[0-9a-f]+ <[^>]*> f123 7000 	cmpi	s0,6432
+[0-9a-f]+ <[^>]*> f123 7020 	cmpi	s0,6432
+[0-9a-f]+ <[^>]*> f123 7040 	cmpi	s0,6432
+[0-9a-f]+ <[^>]*> f123 7060 	cmpi	s0,6432
+[0-9a-f]+ <[^>]*> f123 7080 	cmpi	s0,6432
+[0-9a-f]+ <[^>]*> f123 70a0 	cmpi	s0,6432
+[0-9a-f]+ <[^>]*> f123 70c0 	cmpi	s0,6432
+[0-9a-f]+ <[^>]*> f123 70e0 	cmpi	s0,6432
+[0-9a-f]+ <[^>]*> f123 7800 	sd	s0,6432\(s0\)
+[0-9a-f]+ <[^>]*> f123 8000 	lb	s0,6432\(s0\)
+[0-9a-f]+ <[^>]*> f123 8800 	lh	s0,6432\(s0\)
+[0-9a-f]+ <[^>]*> f123 9000 	lw	s0,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 9020 	lw	s0,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 9040 	lw	s0,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 9060 	lw	s0,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 9080 	lw	s0,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 90a0 	lw	s0,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 90c0 	lw	s0,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 90e0 	lw	s0,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 9800 	lw	s0,6432\(s0\)
+[0-9a-f]+ <[^>]*> f123 a000 	lbu	s0,6432\(s0\)
+[0-9a-f]+ <[^>]*> f123 a800 	lhu	s0,6432\(s0\)
+[0-9a-f]+ <[^>]*> f123 b000 	lw	s0,00001bb8 <foo\+0x1bb8>
+[0-9a-f]+ <[^>]*> f123 b020 	lw	s0,00001bbc <foo\+0x1bbc>
+[0-9a-f]+ <[^>]*> f123 b040 	lw	s0,00001bc0 <foo\+0x1bc0>
+[0-9a-f]+ <[^>]*> f123 b060 	lw	s0,00001bc4 <foo\+0x1bc4>
+[0-9a-f]+ <[^>]*> f123 b080 	lw	s0,00001bc8 <foo\+0x1bc8>
+[0-9a-f]+ <[^>]*> f123 b0a0 	lw	s0,00001bcc <foo\+0x1bcc>
+[0-9a-f]+ <[^>]*> f123 b0c0 	lw	s0,00001bd0 <foo\+0x1bd0>
+[0-9a-f]+ <[^>]*> f123 b0e0 	lw	s0,00001bd4 <foo\+0x1bd4>
+[0-9a-f]+ <[^>]*> f123 b800 	lwu	s0,6432\(s0\)
+[0-9a-f]+ <[^>]*> f123 c000 	sb	s0,6432\(s0\)
+[0-9a-f]+ <[^>]*> f123 c800 	sh	s0,6432\(s0\)
+[0-9a-f]+ <[^>]*> f123 d000 	sw	s0,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 d020 	sw	s0,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 d040 	sw	s0,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 d060 	sw	s0,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 d080 	sw	s0,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 d0a0 	sw	s0,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 d0c0 	sw	s0,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 d0e0 	sw	s0,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 d800 	sw	s0,6432\(s0\)
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e000      	daddu	s0,s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e001      	addu	s0,s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e002      	dsubu	s0,s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e003      	subu	s0,s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e800      	jr	s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e820      	jr	ra
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e840      	jalr	s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e880      	jrc	s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e8a0      	jrc	ra
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e8c0      	jalrc	s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e801      	sdbbp	0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e802      	slt	s0,s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e803      	sltu	s0,s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e804      	sllv	s0,s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e805      	break	0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e806      	srlv	s0,s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e807      	srav	s0,s0
+[0-9a-f]+ <[^>]*> f123 e808 	dsrl	s0,36
+[0-9a-f]+ <[^>]*> f123 e908 	dsrl	s0,36
+[0-9a-f]+ <[^>]*> f123 ea08 	dsrl	s0,36
+[0-9a-f]+ <[^>]*> f123 eb08 	dsrl	s0,36
+[0-9a-f]+ <[^>]*> f123 ec08 	dsrl	s0,36
+[0-9a-f]+ <[^>]*> f123 ed08 	dsrl	s0,36
+[0-9a-f]+ <[^>]*> f123 ee08 	dsrl	s0,36
+[0-9a-f]+ <[^>]*> f123 ef08 	dsrl	s0,36
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e809      	entry
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e829      	entry	ra
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> ed09      	exit	\$f0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> ee09      	exit	\$f0-\$f1
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> ef09      	exit
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e80a      	cmp	s0,s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e80b      	neg	s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e80c      	and	s0,s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e80d      	or	s0,s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e80e      	xor	s0,s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e80f      	not	s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e810      	mfhi	s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e811      	zeb	s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e831      	zeh	s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e851      	zew	s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e891      	seb	s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e8b1      	seh	s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e8d1      	sew	s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e812      	mflo	s0
+[0-9a-f]+ <[^>]*> f123 e813 	dsra	s0,36
+[0-9a-f]+ <[^>]*> f123 e913 	dsra	s0,36
+[0-9a-f]+ <[^>]*> f123 ea13 	dsra	s0,36
+[0-9a-f]+ <[^>]*> f123 eb13 	dsra	s0,36
+[0-9a-f]+ <[^>]*> f123 ec13 	dsra	s0,36
+[0-9a-f]+ <[^>]*> f123 ed13 	dsra	s0,36
+[0-9a-f]+ <[^>]*> f123 ee13 	dsra	s0,36
+[0-9a-f]+ <[^>]*> f123 ef13 	dsra	s0,36
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e814      	dsllv	s0,s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e816      	dsrlv	s0,s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e817      	dsrav	s0,s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e818      	mult	s0,s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e819      	multu	s0,s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e81a      	div	zero,s0,s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e81b      	divu	zero,s0,s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e81c      	dmult	s0,s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e81d      	dmultu	s0,s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e81e      	ddiv	zero,s0,s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> e81f      	ddivu	zero,s0,s0
+[0-9a-f]+ <[^>]*> f123      	extend	0x123
+[0-9a-f]+ <[^>]*> f000      	extend	0x0
+[0-9a-f]+ <[^>]*> f123 f800 	ld	s0,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 f900 	sd	s0,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 fa00 	sd	ra,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 fa20 	sd	ra,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 fa40 	sd	ra,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 fa60 	sd	ra,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 fa80 	sd	ra,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 faa0 	sd	ra,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 fac0 	sd	ra,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 fae0 	sd	ra,6432\(sp\)
+[0-9a-f]+ <[^>]*> f123 fb00 	daddiu	sp,6432
+[0-9a-f]+ <[^>]*> f123 fb20 	daddiu	sp,6432
+[0-9a-f]+ <[^>]*> f123 fb40 	daddiu	sp,6432
+[0-9a-f]+ <[^>]*> f123 fb60 	daddiu	sp,6432
+[0-9a-f]+ <[^>]*> f123 fb80 	daddiu	sp,6432
+[0-9a-f]+ <[^>]*> f123 fba0 	daddiu	sp,6432
+[0-9a-f]+ <[^>]*> f123 fbc0 	daddiu	sp,6432
+[0-9a-f]+ <[^>]*> f123 fbe0 	daddiu	sp,6432
+[0-9a-f]+ <[^>]*> f123 fc00 	ld	s0,00001d50 <foo\+0x1d50>
+[0-9a-f]+ <[^>]*> f123 fd00 	daddiu	s0,6432
+[0-9a-f]+ <[^>]*> f123 fe00 	dla	s0,00001d58 <foo\+0x1d58>
+[0-9a-f]+ <[^>]*> f123 ff00 	daddiu	s0,sp,6432
+	\.\.\.
diff --git a/binutils/testsuite/binutils-all/mips/mips16-extend-insn.s b/binutils/testsuite/binutils-all/mips/mips16-extend-insn.s
new file mode 100644
index 0000000..bb86f22
--- /dev/null
+++ b/binutils/testsuite/binutils-all/mips/mips16-extend-insn.s
@@ -0,0 +1,630 @@
+	.set	mips16
+	.set	noreorder
+foo:
+	extend	0x123		# ADDIUSP
+	addiu	$16, $29, 0
+	extend	0x123
+	addiu	$16, $29, 128
+	extend	0x123
+	addiu	$16, $29, 256
+	extend	0x123
+	addiu	$16, $29, 384
+	extend	0x123
+	addiu	$16, $29, 512
+	extend	0x123
+	addiu	$16, $29, 640
+	extend	0x123
+	addiu	$16, $29, 768
+	extend	0x123
+	addiu	$16, $29, 896
+
+	extend	0x123		# ADDIUPC
+	addiu	$16, $pc, 0
+	extend	0x123
+	addiu	$16, $pc, 128
+	extend	0x123
+	addiu	$16, $pc, 256
+	extend	0x123
+	addiu	$16, $pc, 384
+	extend	0x123
+	addiu	$16, $pc, 512
+	extend	0x123
+	addiu	$16, $pc, 640
+	extend	0x123
+	addiu	$16, $pc, 768
+	extend	0x123
+	addiu	$16, $pc, 896
+
+	extend	0x123		# B
+	b	. + 2
+	extend	0x123
+	b	. + 66
+	extend	0x123
+	b	. + 130
+	extend	0x123
+	b	. + 194
+	extend	0x123
+	b	. + 258
+	extend	0x123
+	b	. + 322
+	extend	0x123
+	b	. + 386
+	extend	0x123
+	b	. + 450
+
+	extend	0x123		# BEQZ
+	beqz	$16, . + 2
+	extend	0x123
+	beqz	$16, . + 66
+	extend	0x123
+	beqz	$16, . + 130
+	extend	0x123
+	beqz	$16, . + 194
+	extend	0x123
+	beqz	$16, . - 254
+	extend	0x123
+	beqz	$16, . - 190
+	extend	0x123
+	beqz	$16, . - 126
+	extend	0x123
+	beqz	$16, . - 62
+
+	extend	0x123		# BNEZ
+	bnez	$16, . + 2
+	extend	0x123
+	bnez	$16, . + 66
+	extend	0x123
+	bnez	$16, . + 130
+	extend	0x123
+	bnez	$16, . + 194
+	extend	0x123
+	bnez	$16, . - 254
+	extend	0x123
+	bnez	$16, . - 190
+	extend	0x123
+	bnez	$16, . - 126
+	extend	0x123
+	bnez	$16, . - 62
+
+	extend	0x123		# SHIFT		# SLL
+	sll	$16, $16, 8
+	extend	0x123
+	sll	$16, $16, 1
+	extend	0x123
+	sll	$16, $16, 2
+	extend	0x123
+	sll	$16, $16, 3
+	extend	0x123
+	sll	$16, $16, 4
+	extend	0x123
+	sll	$16, $16, 5
+	extend	0x123
+	sll	$16, $16, 6
+	extend	0x123
+	sll	$16, $16, 7
+
+	extend	0x123				# DSLL
+	dsll	$16, $16, 8
+	extend	0x123
+	dsll	$16, $16, 1
+	extend	0x123
+	dsll	$16, $16, 2
+	extend	0x123
+	dsll	$16, $16, 3
+	extend	0x123
+	dsll	$16, $16, 4
+	extend	0x123
+	dsll	$16, $16, 5
+	extend	0x123
+	dsll	$16, $16, 6
+	extend	0x123
+	dsll	$16, $16, 7
+
+	extend	0x123				# SRL
+	srl	$16, $16, 8
+	extend	0x123
+	srl	$16, $16, 1
+	extend	0x123
+	srl	$16, $16, 2
+	extend	0x123
+	srl	$16, $16, 3
+	extend	0x123
+	srl	$16, $16, 4
+	extend	0x123
+	srl	$16, $16, 5
+	extend	0x123
+	srl	$16, $16, 6
+	extend	0x123
+	srl	$16, $16, 7
+
+	extend	0x123				# SRA
+	sra	$16, $16, 8
+	extend	0x123
+	sra	$16, $16, 1
+	extend	0x123
+	sra	$16, $16, 2
+	extend	0x123
+	sra	$16, $16, 3
+	extend	0x123
+	sra	$16, $16, 4
+	extend	0x123
+	sra	$16, $16, 5
+	extend	0x123
+	sra	$16, $16, 6
+	extend	0x123
+	sra	$16, $16, 7
+
+	extend	0x123		# LD
+	ld	$16, 0($16)
+
+	extend	0x123		# RRI-A		# ADDIU
+	addiu	$16, $16, 0
+	extend	0x123				# DADDIU
+	daddiu	$16, $16, 0
+
+	extend	0x123		# ADDIU8
+	addiu	$16, 0
+	extend	0x123
+	addiu	$16, 32
+	extend	0x123
+	addiu	$16, 64
+	extend	0x123
+	addiu	$16, 96
+	extend	0x123
+	addiu	$16, -128
+	extend	0x123
+	addiu	$16, -96
+	extend	0x123
+	addiu	$16, -64
+	extend	0x123
+	addiu	$16, -32
+
+	extend	0x123		# SLTI
+	slti	$16, 0
+	extend	0x123
+	slti	$16, 32
+	extend	0x123
+	slti	$16, 64
+	extend	0x123
+	slti	$16, 96
+	extend	0x123
+	slti	$16, 128
+	extend	0x123
+	slti	$16, 160
+	extend	0x123
+	slti	$16, 192
+	extend	0x123
+	slti	$16, 224
+
+	extend	0x123		# SLTIU
+	sltiu	$16, 0
+	extend	0x123
+	sltiu	$16, 32
+	extend	0x123
+	sltiu	$16, 64
+	extend	0x123
+	sltiu	$16, 96
+	extend	0x123
+	sltiu	$16, 128
+	extend	0x123
+	sltiu	$16, 160
+	extend	0x123
+	sltiu	$16, 192
+	extend	0x123
+	sltiu	$16, 224
+
+	extend	0x123		# I8		# BTEQZ
+	bteqz	. + 2
+	extend	0x123
+	bteqz	. + 66
+	extend	0x123
+	bteqz	. + 130
+	extend	0x123
+	bteqz	. + 194
+	extend	0x123
+	bteqz	. - 254
+	extend	0x123
+	bteqz	. - 190
+	extend	0x123
+	bteqz	. - 126
+	extend	0x123
+	bteqz	. - 62
+
+	extend	0x123				# BTNEZ
+	btnez	. + 2
+	extend	0x123
+	btnez	. + 66
+	extend	0x123
+	btnez	. + 130
+	extend	0x123
+	btnez	. + 194
+	extend	0x123
+	btnez	. - 254
+	extend	0x123
+	btnez	. - 190
+	extend	0x123
+	btnez	. - 126
+	extend	0x123
+	btnez	. - 62
+
+	extend	0x123				# SWRASP
+	sw	$31, 0($29)
+	extend	0x123
+	sw	$31, 128($29)
+	extend	0x123
+	sw	$31, 256($29)
+	extend	0x123
+	sw	$31, 512($29)
+	extend	0x123
+	sw	$31, 640($29)
+	extend	0x123
+	sw	$31, 768($29)
+	extend	0x123
+	sw	$31, 896($29)
+	extend	0x123
+	sw	$31, 0($29)
+
+	extend	0x123				# ADJSP
+	addiu	$29, 0
+	extend	0x123
+	addiu	$29, 256
+	extend	0x123
+	addiu	$29, 512
+	extend	0x123
+	addiu	$29, 768
+	extend	0x123
+	addiu	$29, -1024
+	extend	0x123
+	addiu	$29, -768
+	extend	0x123
+	addiu	$29, -512
+	extend	0x123
+	addiu	$29, -256
+
+	extend	0x123				# SVRS		# RESTORE
+	restore	128
+	extend	0x123						# SAVE
+	save	128
+
+	extend	0x123				# MOV32R
+	move	$0, $16
+	extend	0x123
+	move	$0, $17
+
+	extend	0x123				# MOVR32
+	move	$16, $0
+
+	extend	0x123		# LI
+	li	$16, 0
+	extend	0x123
+	li	$16, 32
+	extend	0x123
+	li	$16, 64
+	extend	0x123
+	li	$16, 96
+	extend	0x123
+	li	$16, 128
+	extend	0x123
+	li	$16, 160
+	extend	0x123
+	li	$16, 192
+	extend	0x123
+	li	$16, 224
+
+	extend	0x123		# CMPI
+	cmpi	$16, 0
+	extend	0x123
+	cmpi	$16, 32
+	extend	0x123
+	cmpi	$16, 64
+	extend	0x123
+	cmpi	$16, 96
+	extend	0x123
+	cmpi	$16, 128
+	extend	0x123
+	cmpi	$16, 160
+	extend	0x123
+	cmpi	$16, 192
+	extend	0x123
+	cmpi	$16, 224
+
+	extend	0x123		# SD
+	sd	$16, 0($16)
+
+	extend	0x123		# LB
+	lb	$16, 0($16)
+
+	extend	0x123		# LH
+	lh	$16, 0($16)
+
+	extend	0x123		# LWSP
+	lw	$16, 0($29)
+	extend	0x123
+	lw	$16, 128($29)
+	extend	0x123
+	lw	$16, 256($29)
+	extend	0x123
+	lw	$16, 384($29)
+	extend	0x123
+	lw	$16, 512($29)
+	extend	0x123
+	lw	$16, 640($29)
+	extend	0x123
+	lw	$16, 768($29)
+	extend	0x123
+	lw	$16, 896($29)
+
+	extend	0x123		# LW
+	lw	$16, 0($16)
+
+	extend	0x123		# LBU
+	lbu	$16, 0($16)
+
+	extend	0x123		# LHU
+	lhu	$16, 0($16)
+
+	extend	0x123		# LWPC
+	lw	$16, 0($pc)
+	extend	0x123
+	lw	$16, 128($pc)
+	extend	0x123
+	lw	$16, 256($pc)
+	extend	0x123
+	lw	$16, 384($pc)
+	extend	0x123
+	lw	$16, 512($pc)
+	extend	0x123
+	lw	$16, 640($pc)
+	extend	0x123
+	lw	$16, 768($pc)
+	extend	0x123
+	lw	$16, 896($pc)
+
+	extend	0x123		# LWU
+	lwu	$16, 0($16)
+
+	extend	0x123		# SB
+	sb	$16, 0($16)
+
+	extend	0x123		# SH
+	sh	$16, 0($16)
+
+	extend	0x123		# SWSP
+	sw	$16, 0($29)
+	extend	0x123
+	sw	$16, 128($29)
+	extend	0x123
+	sw	$16, 256($29)
+	extend	0x123
+	sw	$16, 384($29)
+	extend	0x123
+	sw	$16, 512($29)
+	extend	0x123
+	sw	$16, 640($29)
+	extend	0x123
+	sw	$16, 768($29)
+	extend	0x123
+	sw	$16, 896($29)
+
+	extend	0x123		# SW
+	sw	$16, 0($16)
+
+	extend	0x123		# RRR		# DADDU
+	daddu	$16, $16, $16
+
+	extend	0x123				# ADDU
+	addu	$16, $16, $16
+
+	extend	0x123				# DSUBU
+	dsubu	$16, $16, $16
+
+	extend	0x123				# SUBU
+	subu	$16, $16, $16
+
+	extend	0x123		# RR		# J(AL)R(C)	# JR rx
+	jr	$16
+	extend	0x123						# JR ra
+	jr	$31
+	extend	0x123						# JALR
+	jalr	$16
+	extend	0x123						# JRC rx
+	jrc	$16
+	extend	0x123						# JRC ra
+	jrc	$31
+	extend	0x123						# JALRC
+	jalrc	$16
+
+	extend	0x123				# SDBBP
+	sdbbp	0
+
+	extend	0x123				# SLT
+	slt	$16, $16
+
+	extend	0x123				# SLTU
+	sltu	$16, $16
+
+	extend	0x123				# SLLV
+	sllv	$16, $16
+
+	extend	0x123				# BREAK
+	break	0
+
+	extend	0x123				# SRLV
+	srlv	$16, $16
+
+	extend	0x123				# SRAV
+	srav	$16, $16
+
+	extend	0x123				# DSRL
+	dsrl	$16, 8
+	extend	0x123
+	dsrl	$16, 1
+	extend	0x123
+	dsrl	$16, 2
+	extend	0x123
+	dsrl	$16, 3
+	extend	0x123
+	dsrl	$16, 4
+	extend	0x123
+	dsrl	$16, 5
+	extend	0x123
+	dsrl	$16, 6
+	extend	0x123
+	dsrl	$16, 7
+
+	extend	0x123				# ENTRY/EXIT
+	entry
+	extend	0x123
+	entry	$31
+	extend	0x123
+	exit	$f0
+	extend	0x123
+	exit	$f0-$f1
+	extend	0x123
+	exit
+
+	extend	0x123				# CMP
+	cmp	$16, $16
+
+	extend	0x123				# NEG
+	neg	$16, $16
+
+	extend	0x123				# AND
+	and	$16, $16
+
+	extend	0x123				# OR
+	or	$16, $16
+
+	extend	0x123				# XOR
+	xor	$16, $16
+
+	extend	0x123				# NOT
+	not	$16, $16
+
+	extend	0x123				# MFHI
+	mfhi	$16
+
+	extend	0x123				# CNVT		# ZEB
+	zeb	$16
+	extend	0x123						# ZEH
+	zeh	$16
+	extend	0x123						# ZEW
+	zew	$16
+	extend	0x123						# SEB
+	seb	$16
+	extend	0x123						# SEH
+	seh	$16
+	extend	0x123						# SEW
+	sew	$16
+
+	extend	0x123				# MFLO
+	mflo	$16
+
+	extend	0x123				# DSRA
+	dsra	$16, 8
+	extend	0x123
+	dsra	$16, 1
+	extend	0x123
+	dsra	$16, 2
+	extend	0x123
+	dsra	$16, 3
+	extend	0x123
+	dsra	$16, 4
+	extend	0x123
+	dsra	$16, 5
+	extend	0x123
+	dsra	$16, 6
+	extend	0x123
+	dsra	$16, 7
+
+	extend	0x123				# DSLLV
+	dsllv	$16, $16
+
+	extend	0x123				# DSRLV
+	dsrlv	$16, $16
+
+	extend	0x123				# DSRAV
+	dsrav	$16, $16
+
+	extend	0x123				# MULT
+	mult	$16, $16
+
+	extend	0x123				# MULTU
+	multu	$16, $16
+
+	extend	0x123				# DIV
+	div	$0, $16, $16
+
+	extend	0x123				# DIVU
+	divu	$0, $16, $16
+
+	extend	0x123				# DMULT
+	dmult	$16, $16
+
+	extend	0x123				# DMULTU
+	dmultu	$16, $16
+
+	extend	0x123				# DDIV
+	ddiv	$0, $16, $16
+
+	extend	0x123				# DDIVU
+	ddivu	$0, $16, $16
+
+	extend	0x123		# EXTEND
+	extend	0
+
+	extend	0x123		# I64		# LDSP
+	ld	$16, 0($29)
+
+	extend	0x123				# SDSP
+	sd	$16, 0($29)
+
+	extend	0x123				# SDRASP
+	sd	$31, 0($29)
+	extend	0x123
+	sd	$31, 256($29)
+	extend	0x123
+	sd	$31, 512($29)
+	extend	0x123
+	sd	$31, 768($29)
+	extend	0x123
+	sd	$31, 1024($29)
+	extend	0x123
+	sd	$31, 1280($29)
+	extend	0x123
+	sd	$31, 1536($29)
+	extend	0x123
+	sd	$31, 1792($29)
+
+	extend	0x123				# DADJSP
+	daddiu	$29, 0
+	extend	0x123
+	daddiu	$29, 256
+	extend	0x123
+	daddiu	$29, 512
+	extend	0x123
+	daddiu	$29, 768
+	extend	0x123
+	daddiu	$29, -1024
+	extend	0x123
+	daddiu	$29, -768
+	extend	0x123
+	daddiu	$29, -512
+	extend	0x123
+	daddiu	$29, -256
+
+	extend	0x123				# LDPC
+	ld	$16, 0($pc)
+
+	extend	0x123				# DADDIU5
+	daddiu	$16, 0
+
+	extend	0x123				# DADDIUPC
+	daddiu	$16, $pc, 0
+
+	extend	0x123				# DADDIUSP
+	daddiu	$16, $sp, 0
+
+# Force some (non-delay-slot) zero bytes, to make 'objdump' print ...
+	.align	4, 0
+	.space	16