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| author | Maciej W. Rozycki <macro@imgtec.com> | 2016-12-20 02:03:40 +0000 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@imgtec.com> | 2016-12-20 11:56:32 +0000 |
| commit | 7fd5392005624f8b0522d881aa94bbb470d68cd7 (patch) | |
| tree | 680a9185f2e3f2c781b08b445357561cffc94077 /binutils | |
| parent | 4ebce1a0a5911e71aa2d00932ffb2126ff1f3633 (diff) | |
| download | gdb-7fd5392005624f8b0522d881aa94bbb470d68cd7.zip gdb-7fd5392005624f8b0522d881aa94bbb470d68cd7.tar.gz gdb-7fd5392005624f8b0522d881aa94bbb470d68cd7.tar.bz2 | |
MIPS16: Switch to 32-bit opcode table interpretation
Switch to 32-bit MIPS16 opcode table entry interpretation, similar to
how the microMIPS opcode table is handled, for both the `match' and
`mask' fields, removing special casing for JAL and JALX instructions and
their `a' and `i' operand codes throughout, while retaining automatic
processing of extendable opcodes in assembly and disassembly.
In assembly disallow size enforcement suffixes as appropriate: `.t' for
both 32-bit instructions and macros and `.e' for macros only, making
macro handling consistent with the microMIPS instruction set.
In disassembly fully decode EXTEND prefixes prepended to unsupported
instruction encodings (according to the ISA selection) rather than
dumping them as hexadecimal data along with the following instruction,
removing all special casing for the EXTEND prefix and making its
handling rely on its opcode table entry, except where it is considered a
part of an extendable instruction.
include/
* opcode/mips.h (mips_opcode_32bit_p): New inline function.
gas/
* config/tc-mips.c (micromips_insn_length): Use
`mips_opcode_32bit_p'.
(is_size_valid): Adjust description.
(is_size_valid_16): New function.
(validate_mips_insn): Use `mips_opcode_32bit_p' in MIPS16
operand decoding.
(validate_mips16_insn): Remove `a' and `i' operand code special
casing, use `mips_opcode_32bit_p' to determine instruction
width.
(append_insn): Adjust forced MIPS16 instruction size
determination.
(match_mips16_insn): Likewise. Don't shift the instruction's
opcode with the `a' and `i' operand codes. Use
`mips_opcode_32bit_p' in operand decoding.
(match_mips16_insns): Check for forced instruction size's
validity.
(mips16_ip): Don't force instruction size in the `noautoextend'
mode.
* testsuite/gas/mips/mips16-jal-e.d: New test.
* testsuite/gas/mips/mips16-jal-t.d: New test.
* testsuite/gas/mips/mips16-macro-e.d: New test.
* testsuite/gas/mips/mips16-macro-t.d: New test.
* testsuite/gas/mips/mips16-jal-t.l: New stderr output.
* testsuite/gas/mips/mips16-macro-e.l: New stderr output.
* testsuite/gas/mips/mips16-macro-t.l: New stderr output.
* testsuite/gas/mips/mips16-jal-e.s: New test source.
* testsuite/gas/mips/mips16-jal-t.s: New test source.
* testsuite/gas/mips/mips16-macro-e.s: New test source.
* testsuite/gas/mips/mips16-macro-t.s: New test source.
* testsuite/gas/mips/mips.exp: Run the new tests.
opcodes/
* mips-dis.c (print_mips16_insn_arg): Always handle `extend' and
`insn' together, with `extend' as the high-order 16 bits.
(match_kind): New enum.
(print_insn_mips16): Rework for 32-bit instruction matching.
Do not dump EXTEND prefixes here.
* mips16-opc.c (mips16_opcodes): Move "extend" entry to the end.
Recode `match' and `mask' fields as 32-bit in absolute "jal" and
"jalx" entries.
binutils/
* testsuite/binutils-all/mips/mips16-extend-noinsn.d: Adjust
test for separate EXTEND prefix disassembly.
Diffstat (limited to 'binutils')
| -rw-r--r-- | binutils/ChangeLog | 5 | ||||
| -rw-r--r-- | binutils/testsuite/binutils-all/mips/mips16-extend-noinsn.d | 18 |
2 files changed, 17 insertions, 6 deletions
diff --git a/binutils/ChangeLog b/binutils/ChangeLog index fd86ed5..6e9de9b 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,3 +1,8 @@ +2016-12-20 Maciej W. Rozycki <macro@imgtec.com> + + * testsuite/binutils-all/mips/mips16-extend-noinsn.d: Adjust + test for separate EXTEND prefix disassembly. + 2016-12-20 Andrew Waterman <andrew@sifive.com> * readelf.c (get_machine_flags): Use diff --git a/binutils/testsuite/binutils-all/mips/mips16-extend-noinsn.d b/binutils/testsuite/binutils-all/mips/mips16-extend-noinsn.d index 5694de6..398f5a5 100644 --- a/binutils/testsuite/binutils-all/mips/mips16-extend-noinsn.d +++ b/binutils/testsuite/binutils-all/mips/mips16-extend-noinsn.d @@ -17,12 +17,18 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> f432 extend 0x432 [0-9a-f]+ <[^>]*> 1c00 0000 jalx 00000000 <foo> [0-9a-f]+ <[^>]*> 6500 nop -[0-9a-f]+ <[^>]*> f123 6621 0xf123 0x6621 -[0-9a-f]+ <[^>]*> f456 e935 0xf456 0xe935 -[0-9a-f]+ <[^>]*> f765 ea60 0xf765 0xea60 -[0-9a-f]+ <[^>]*> f432 ece0 0xf432 0xece0 -[0-9a-f]+ <[^>]*> f5aa e971 0xf5aa 0xe971 -[0-9a-f]+ <[^>]*> f655 ebf1 0xf655 0xebf1 +[0-9a-f]+ <[^>]*> f123 extend 0x123 +[0-9a-f]+ <[^>]*> 6621 0x6621 +[0-9a-f]+ <[^>]*> f456 extend 0x456 +[0-9a-f]+ <[^>]*> e935 0xe935 +[0-9a-f]+ <[^>]*> f765 extend 0x765 +[0-9a-f]+ <[^>]*> ea60 0xea60 +[0-9a-f]+ <[^>]*> f432 extend 0x432 +[0-9a-f]+ <[^>]*> ece0 0xece0 +[0-9a-f]+ <[^>]*> f5aa extend 0x5aa +[0-9a-f]+ <[^>]*> e971 0xe971 +[0-9a-f]+ <[^>]*> f655 extend 0x655 +[0-9a-f]+ <[^>]*> ebf1 0xebf1 [0-9a-f]+ <[^>]*> 6621 0x6621 [0-9a-f]+ <[^>]*> e935 0xe935 [0-9a-f]+ <[^>]*> ea60 0xea60 |