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| author | Maciej W. Rozycki <macro@imgtec.com> | 2017-05-02 11:53:30 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@imgtec.com> | 2017-05-02 11:58:44 +0100 |
| commit | a4ddc54ec1cd187c844ca631fe0315bf1d78e96f (patch) | |
| tree | d13d98c24eb7b60d6203e0adb8bc6edf50b9519c /binutils | |
| parent | 39ff1b79f687b65f4144ddb379f22587003443fb (diff) | |
| download | gdb-a4ddc54ec1cd187c844ca631fe0315bf1d78e96f.zip gdb-a4ddc54ec1cd187c844ca631fe0315bf1d78e96f.tar.gz gdb-a4ddc54ec1cd187c844ca631fe0315bf1d78e96f.tar.bz2 | |
MIPS16/opcodes: Keep the LSB of PC-relative offsets in disassembly
Correct the disassembly of the PC-relative immediate argument of the
MIPS16 synthetic LA, LW, DLA and LD instructions and do not mask the
LSB, which in this case is a part of the data address rather than the
ISA bit and has to be fully presented.
opcodes/
* mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
and branches and not synthetic data instructions.
binutils/
* testsuite/binutils-all/mips/mips16-undecoded.d: Adjust the
disassembly of PC-relative LA and LW synthetic instructions.
Diffstat (limited to 'binutils')
| -rw-r--r-- | binutils/ChangeLog | 5 | ||||
| -rw-r--r-- | binutils/testsuite/binutils-all/mips/mips16-undecoded.d | 20 |
2 files changed, 15 insertions, 10 deletions
diff --git a/binutils/ChangeLog b/binutils/ChangeLog index 5fdcd4d..aef436d 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,3 +1,8 @@ +2017-05-02 Maciej W. Rozycki <macro@imgtec.com> + + * testsuite/binutils-all/mips/mips16-undecoded.d: Adjust the + disassembly of PC-relative LA and LW synthetic instructions. + 2017-05-02 Nick Clifton <nickc@redhat.com> PR 21440 diff --git a/binutils/testsuite/binutils-all/mips/mips16-undecoded.d b/binutils/testsuite/binutils-all/mips/mips16-undecoded.d index 42a5cdf..b455419 100644 --- a/binutils/testsuite/binutils-all/mips/mips16-undecoded.d +++ b/binutils/testsuite/binutils-all/mips/mips16-undecoded.d @@ -11,11 +11,11 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> f008 0231 addiu v0,sp,16401 [0-9a-f]+ <[^>]*> f008 0251 addiu v0,sp,16401 [0-9a-f]+ <[^>]*> f008 0291 addiu v0,sp,16401 -[0-9a-f]+ <[^>]*> f008 0a11 la v0,00004024 <foo\+0x4024> -[0-9a-f]+ <[^>]*> f008 0a11 la v0,00004028 <foo\+0x4028> -[0-9a-f]+ <[^>]*> f008 0a31 la v0,0000402c <foo\+0x402c> -[0-9a-f]+ <[^>]*> f008 0a51 la v0,00004030 <foo\+0x4030> -[0-9a-f]+ <[^>]*> f008 0a91 la v0,00004034 <foo\+0x4034> +[0-9a-f]+ <[^>]*> f008 0a11 la v0,00004025 <foo\+0x4025> +[0-9a-f]+ <[^>]*> f008 0a11 la v0,00004029 <foo\+0x4029> +[0-9a-f]+ <[^>]*> f008 0a31 la v0,0000402d <foo\+0x402d> +[0-9a-f]+ <[^>]*> f008 0a51 la v0,00004031 <foo\+0x4031> +[0-9a-f]+ <[^>]*> f008 0a91 la v0,00004035 <foo\+0x4035> [0-9a-f]+ <[^>]*> f008 1011 b 0000804e <foo\+0x804e> [0-9a-f]+ <[^>]*> f008 1011 b 00008052 <foo\+0x8052> [0-9a-f]+ <[^>]*> f008 1031 b 00008056 <foo\+0x8056> @@ -64,11 +64,11 @@ Disassembly of section \.text: [0-9a-f]+ <[^>]*> f008 9231 lw v0,16401\(sp\) [0-9a-f]+ <[^>]*> f008 9251 lw v0,16401\(sp\) [0-9a-f]+ <[^>]*> f008 9291 lw v0,16401\(sp\) -[0-9a-f]+ <[^>]*> f008 b211 lw v0,000040f8 <foo\+0x40f8> -[0-9a-f]+ <[^>]*> f008 b211 lw v0,000040fc <foo\+0x40fc> -[0-9a-f]+ <[^>]*> f008 b231 lw v0,00004100 <foo\+0x4100> -[0-9a-f]+ <[^>]*> f008 b251 lw v0,00004104 <foo\+0x4104> -[0-9a-f]+ <[^>]*> f008 b291 lw v0,00004108 <foo\+0x4108> +[0-9a-f]+ <[^>]*> f008 b211 lw v0,000040f9 <foo\+0x40f9> +[0-9a-f]+ <[^>]*> f008 b211 lw v0,000040fd <foo\+0x40fd> +[0-9a-f]+ <[^>]*> f008 b231 lw v0,00004101 <foo\+0x4101> +[0-9a-f]+ <[^>]*> f008 b251 lw v0,00004105 <foo\+0x4105> +[0-9a-f]+ <[^>]*> f008 b291 lw v0,00004109 <foo\+0x4109> [0-9a-f]+ <[^>]*> f008 d211 sw v0,16401\(sp\) [0-9a-f]+ <[^>]*> f008 d211 sw v0,16401\(sp\) [0-9a-f]+ <[^>]*> f008 d231 sw v0,16401\(sp\) |