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authorJim Wilson <jimw@sifive.com>2018-05-18 14:03:18 -0700
committerJim Wilson <jimw@sifive.com>2018-05-18 14:03:18 -0700
commit7f99954970001cfc1b155d877ac2966d77e2c647 (patch)
tree585e05cfeb9fc8e287b7b607bc27851b90ebf30c /binutils
parent400174b12a46fffbfad7c2504c33bb3ac29f3ef9 (diff)
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RISC-V: Add RV32E support.
Kito Cheng <kito.cheng@gmail.com> Monk Chiang <sh.chiang04@gmail.com> bfd/ * elfnn-riscv.c (_bfd_riscv_elf_merge_private_bfd_data): Handle EF_RISCV_RVE. binutils/ * readelf.c (get_machine_flags): Handle EF_RISCV_RVE. gas/ * config/tc-riscv.c (rve_abi): New. (riscv_set_options): Add rve field. Initialize it. (riscv_set_rve) New function. (riscv_set_arch): Support 'e' ISA subset. (reg_lookup_internal): If rve, check register is available. (riscv_set_abi): New parameter rve. (md_parse_option): Pass new argument to riscv_set_abi. (riscv_after_parse_args): Call riscv_set_rve. If rve_abi, set EF_RISCV_RVE. * doc/c-riscv.texi (-mabi): Document new ilp32e argument. include/ * elf/riscv.h (EF_RISCV_RVE): New define.
Diffstat (limited to 'binutils')
-rw-r--r--binutils/ChangeLog4
-rw-r--r--binutils/readelf.c3
2 files changed, 7 insertions, 0 deletions
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index fd77f44..2943b1d 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,7 @@
+2018-05-18 Kito Cheng <kito.cheng@gmail.com>
+
+ * readelf.c (get_machine_flags): Handle EF_RISCV_RVE.
+
2018-05-18 John Darrington <john@darrington.wattle.id.au>
* readelf.c: Add support for s12z architecture.
diff --git a/binutils/readelf.c b/binutils/readelf.c
index 6a9319f..8335538 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -3472,6 +3472,9 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine)
if (e_flags & EF_RISCV_RVC)
strcat (buf, ", RVC");
+ if (e_flags & EF_RISCV_RVE)
+ strcat (buf, ", RVE");
+
switch (e_flags & EF_RISCV_FLOAT_ABI)
{
case EF_RISCV_FLOAT_ABI_SOFT: