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authorTamar Christina <tamar.christina@arm.com>2020-01-27 10:40:02 +0000
committerTamar Christina <tamar.christina@arm.com>2020-01-27 10:55:41 +0000
commit7568c93bf95a518797dfb2987b04911164c14a36 (patch)
tree10b4933b73b7a607b53f2f76f5fb298f67a8a018 /binutils/testsuite
parent168f8c6ba008bed9fcc2fe7098416f608e4419af (diff)
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AArch64: Fix cfinv disassembly issues
This fixes the preferred disassembly for cfinv. The Armv8.4-a instruction overlaps with the possible encoding space for msr. This because msr allows you to use unallocated encoding space using the general sA_B_cC_cD_E form. However when an encoding does become allocated then we need to ensure that it's used as the preferred disassembly. The problem with cfinv is that its mask has all bits sets because it has no arguments. This causes issues for the Alias resolver in gas as it uses the mask to build alias graph. In this case it can't do it since it thinks almost everything would alias with cfinv. So instead we can only fix this by moving cfinv before msr. gas/ChangeLog: PR 25403 * testsuite/gas/aarch64/armv8_4-a.d: Add cfinv. * testsuite/gas/aarch64/armv8_4-a.s: Likewise. opcodes/ChangeLog: PR 25403 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv. * aarch64-asm-2.c: Regenerate * aarch64-dis-2.c: Likewise. * aarch64-opc-2.c: Likewise.
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