Add new option to objcopy: --verilog-data-width. Use this option to set the size of byte bundles generated in verilog format files.

	PR 19921
binutils* objcopy.c: Add new option --verilog-data-width.  Use it to set
	the value of VerilogDataWidth.
	* doc/binutils.texi: Document the new option.
	* testsuite/binutils-all/objcopy.exp: Run tests of new option.
	* testsuite/binutils-all/verilog-1.hex: New file.
	* testsuite/binutils-all/verilog-2.hex: New file.
	* testsuite/binutils-all/verilog-4.hex: New file.
	* testsuite/binutils-all/verilog-8.hex: New file.
	* NEWS: Mention the new feature.

bfd	* verilog.c: (VerilogDataWidth): New variable.
	(verilog_write_record): Emit bytes in VerilogDataWidth bundles.

5 files changed, 65 insertions, 0 deletions

diff --git a/binutils/testsuite/binutils-all/objcopy.exp b/binutils/testsuite/binutils-all/objcopy.exp
index 921e6a2..ba5ddc8 100644
--- a/binutils/testsuite/binutils-all/objcopy.exp
+++ b/binutils/testsuite/binutils-all/objcopy.exp
@@ -102,6 +102,50 @@ proc objcopy_test {testname srcfile} {
 
 objcopy_test "simple copy" bintest.s
 
+# Test verilog data width
+proc objcopy_test_verilog {testname} {
+    global OBJCOPY
+    global OBJCOPYFLAGS
+    global srcdir
+    global subdir
+    global copyfile
+    set binfile tmpdir/verilogtest.o
+    set verilog tmpdir/verilog
+
+    set got [binutils_assemble $srcdir/$subdir/verilogtest.s $binfile]
+    if {![binutils_assemble $srcdir/$subdir/verilogtest.s $binfile]} then {
+	unresolved "objcopy ($testname)"
+	return
+    }
+
+    set got [binutils_run $OBJCOPY "-O verilog $binfile $verilog"]
+    if ![string equal "" $got] then {
+	fail "objcopy ($testname)"
+    }
+
+    set got [binutils_run $OBJCOPY "-O verilog --verilog-data-width 0 $binfile $verilog-0.hex"]
+    if ![regexp "verilog data width must be at least 1 byte" $got] then {
+	fail "objcopy ($testname 0) {$got}"
+    } else {
+	pass "objcopy ($testname 0)"
+    }
+
+    foreach width {1 2 4 8} {
+	set got [binutils_run $OBJCOPY "-O verilog --verilog-data-width $width $binfile $verilog-$width.hex"]
+	if ![string equal "" $got] then {
+	    fail "objcopy ($testname $width)"
+	}
+        send_log "regexp_diff $verilog-$width.hex $srcdir/$subdir/verilog-$width.hex\n"
+	if {! [regexp_diff "$verilog-$width.hex" "$srcdir/$subdir/verilog-$width.hex"]} {
+	    pass "objcopy ($testname $width)"
+	} else {
+	    fail "objcopy ($testname $width)"
+	}
+    }
+}
+
+objcopy_test_verilog "verilog data width"
+
 if { [file exists $tempfile] } {
     # Test reversing bytes in a section.
 
diff --git a/binutils/testsuite/binutils-all/verilog-1.hex b/binutils/testsuite/binutils-all/verilog-1.hex
new file mode 100644
index 0000000..0a59a58
--- /dev/null
+++ b/binutils/testsuite/binutils-all/verilog-1.hex
@@ -0,0 +1,5 @@
+@00000000
+0[134] 0[234] 0[123] 0[124] 00 00 00 00.*
+@000000..
+0[02] 00 0[02] 0[02].*
+#pass
diff --git a/binutils/testsuite/binutils-all/verilog-2.hex b/binutils/testsuite/binutils-all/verilog-2.hex
new file mode 100644
index 0000000..f1e0d7a
--- /dev/null
+++ b/binutils/testsuite/binutils-all/verilog-2.hex
@@ -0,0 +1,5 @@
+@00000000
+0[1234]0[1234] 0[1234]0[1234] 0000 0000.*
+@000000..
+0[02]0[02] 0[02]0[02].*
+#pass
diff --git a/binutils/testsuite/binutils-all/verilog-4.hex b/binutils/testsuite/binutils-all/verilog-4.hex
new file mode 100644
index 0000000..119f009
--- /dev/null
+++ b/binutils/testsuite/binutils-all/verilog-4.hex
@@ -0,0 +1,6 @@
+@00000000
+0[134]0[234]0[123]0[124] 00000000.*
+@000000..
+0[20]000[02]0[02].*
+#pass
+
diff --git a/binutils/testsuite/binutils-all/verilog-8.hex b/binutils/testsuite/binutils-all/verilog-8.hex
new file mode 100644
index 0000000..567d33e
--- /dev/null
+++ b/binutils/testsuite/binutils-all/verilog-8.hex
@@ -0,0 +1,5 @@
+@00000000
+0[0134]0[0234]0[0123]0[0124]0[40]0[30]0[20]0[10].*
+@000000..
+0[20]000[02]0[20].*
+#pass