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| author | Nick Clifton <nickc@redhat.com> | 2022-12-01 13:09:26 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2022-12-01 13:09:26 +0000 |
| commit | 6ef35c04dffe685ece08212201c4c032baf8aa86 (patch) | |
| tree | 3eba01220e92f2f24152d4ad94f4be8c45c9f53b /binutils/objcopy.c | |
| parent | 7505bb034c7c8a3d9ecf34e22777114c8bc4a93e (diff) | |
| download | gdb-6ef35c04dffe685ece08212201c4c032baf8aa86.zip gdb-6ef35c04dffe685ece08212201c4c032baf8aa86.tar.gz gdb-6ef35c04dffe685ece08212201c4c032baf8aa86.tar.bz2 | |
Fix verilog output when the width is > 1.
PR 25202
bfd * bfd.c (VerilogDataEndianness): New variable.
(verilog_write_record): Use VerilogDataEndianness, if set, to
choose the endianness of the output.
(verilog_write_section): Adjust the address by the data width.
binutils* objcopy.c (copy_object): Set VerilogDataEndianness to the
endianness of the input file.
(copy_main): Verifiy the value set by the --verilog-data-width
option.
* testsuite/binutils-all/objcopy.exp: Add tests of the new behaviour.
* testsuite/binutils-all/verilog-I4.hex: New file.
Diffstat (limited to 'binutils/objcopy.c')
| -rw-r--r-- | binutils/objcopy.c | 25 |
1 files changed, 23 insertions, 2 deletions
diff --git a/binutils/objcopy.c b/binutils/objcopy.c index 3d88624..6814e20 100644 --- a/binutils/objcopy.c +++ b/binutils/objcopy.c @@ -546,6 +546,11 @@ extern bool _bfd_srec_forceS3; the --verilog-data-width parameter. */ extern unsigned int VerilogDataWidth; +/* Endianness of data for verilog output. + This variable is declared in bfd/verilog.c and is set in the + copy_object() function. */ +extern enum bfd_endian VerilogDataEndianness; + /* Forward declarations. */ static void setup_section (bfd *, asection *, void *); static void setup_bfd_headers (bfd *, bfd *); @@ -2655,6 +2660,12 @@ copy_object (bfd *ibfd, bfd *obfd, const bfd_arch_info_type *input_arch) return false; } + /* Set the Verilog output endianness based upon the input file's + endianness. We may not be producing verilog format output, + but testing this just adds extra code this is not really + necessary. */ + VerilogDataEndianness = ibfd->xvec->byteorder; + if (bfd_get_flavour (ibfd) != bfd_target_elf_flavour) { if ((do_debug_sections & compress) != 0 @@ -5847,8 +5858,18 @@ copy_main (int argc, char *argv[]) case OPTION_VERILOG_DATA_WIDTH: VerilogDataWidth = parse_vma (optarg, "--verilog-data-width"); - if (VerilogDataWidth < 1) - fatal (_("verilog data width must be at least 1 byte")); + switch (VerilogDataWidth) + { + case 1: + case 2: + case 4: + case 8: + case 16: /* We do not support widths > 16 because the verilog + data is handled internally in 16 byte wide packets. */ + break; + default: + fatal (_("error: verilog data width must be 1, 2, 4, 8 or 16")); + } break; case 0: |