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| author | Maciej W. Rozycki <macro@imgtec.com> | 2017-06-30 07:21:56 +0100 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@imgtec.com> | 2017-06-30 07:21:56 +0100 |
| commit | f5b2fd523f8f180e11f77b84a107279c562672cd (patch) | |
| tree | 531ff5dcc9ae39d065a05f96655363d3ad5895d1 /binutils/NEWS | |
| parent | 9785fc2a4d220322ce6cd1d79e768345ea5234d2 (diff) | |
| download | gdb-f5b2fd523f8f180e11f77b84a107279c562672cd.zip gdb-f5b2fd523f8f180e11f77b84a107279c562672cd.tar.gz gdb-f5b2fd523f8f180e11f77b84a107279c562672cd.tar.bz2 | |
MIPS: Add microMIPS R5 support
Add base microMIPS Release 5 ISA support and the ERETNC instruction in
particular, as per the architecture specifications[1][2].
Most of this change by Andrew Bennett.
References:
[1] "MIPS Architecture for Programmers Volume II-B: The microMIPS32
Instruction Set", MIPS Technologies, Inc., Document Number: MD00582,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", pp. 266-267
[2] "MIPS Architecture for Programmers Volume II-B: The microMIPS64
Instruction Set", MIPS Technologies, Inc., Document Number: MD00594,
Revision 5.04, January 15, 2014, Section 5.5 "Recoded 32-Bit
Instructions", pp. 326-327
binutils/
* NEWS: Mention microMIPS Release 5 ISA support.
opcodes/
* micromips-opc.c (I36): New macro.
(micromips_opcodes): Add "eretnc".
gas/
* testsuite/gas/mips/micromips@r5.d: New test.
* testsuite/gas/mips/mips.exp: Run the new test.
Diffstat (limited to 'binutils/NEWS')
| -rw-r--r-- | binutils/NEWS | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/binutils/NEWS b/binutils/NEWS index b49e2d3..f8f33c7 100644 --- a/binutils/NEWS +++ b/binutils/NEWS @@ -1,5 +1,8 @@ -*- text -*- +* The MIPS port now supports the microMIPS Release 5 ISA for assembly and + disassembly. + * The MIPS port now supports the Imagination interAptiv MR2 processor, which implements the MIPS32r3 ISA, the MIPS16e2 ASE as well as a couple of implementation-specific regular MIPS and MIPS16e2 ASE instructions. |