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authorNick Clifton <nickc@redhat.com>2022-12-01 13:09:26 +0000
committerNick Clifton <nickc@redhat.com>2022-12-01 13:09:26 +0000
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parent7505bb034c7c8a3d9ecf34e22777114c8bc4a93e (diff)
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Fix verilog output when the width is > 1.
PR 25202 bfd * bfd.c (VerilogDataEndianness): New variable. (verilog_write_record): Use VerilogDataEndianness, if set, to choose the endianness of the output. (verilog_write_section): Adjust the address by the data width. binutils* objcopy.c (copy_object): Set VerilogDataEndianness to the endianness of the input file. (copy_main): Verifiy the value set by the --verilog-data-width option. * testsuite/binutils-all/objcopy.exp: Add tests of the new behaviour. * testsuite/binutils-all/verilog-I4.hex: New file.
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@@ -1,3 +1,13 @@
+2022-12-01 Nick Clifton <nickc@redhat.com>
+
+ PR 25202
+ * objcopy.c (copy_object): Set VerilogDataEndianness to the
+ endianness of the input file.
+ (copy_main): Verifiy the value set by the --verilog-data-width
+ option.
+ * testsuite/binutils-all/objcopy.exp: Add tests of the new behaviour.
+ * testsuite/binutils-all/verilog-I4.hex: New file.
+
2022-11-21 Nick Clifton <nickc@redhat.com>
PR 29764