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| author | Xiao Zeng <zengxiao@eswincomputing.com> | 2023-12-15 09:57:09 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2023-12-15 10:07:14 +0800 |
| commit | b291c12e8d08d01e598526ac6c9cb20543f41293 (patch) | |
| tree | 14c678815bb9b42594720f0d44c6418846558c97 /bfd | |
| parent | bf19fc7706c5c4bc942203af7a1df43cf392f89b (diff) | |
| download | gdb-b291c12e8d08d01e598526ac6c9cb20543f41293.zip gdb-b291c12e8d08d01e598526ac6c9cb20543f41293.tar.gz gdb-b291c12e8d08d01e598526ac6c9cb20543f41293.tar.bz2 | |
RISC-V: Imply 'Zicntr' and 'Zihpm' implicitly depended on 'Zicsr'
This commit adds support for ratified extensions:
'Zicntr' and 'Zihpm', Which are all implicitly depend on 'Zicsr'.
This is based on:
<https://github.com/riscv/riscv-isa-manual/releases/download/riscv-isa-release-056b6ff-2023-10-02/unpriv-isa-asciidoc.pdf>
bfd/ChangeLog:
* elfxx-riscv.c: Add 'Zicntr' and 'Zihpm' -> 'Zicsr'.
(riscv_supported_std_z_ext) Add 'Zicntr' and 'Zihpm' to the list.
Diffstat (limited to 'bfd')
| -rw-r--r-- | bfd/elfxx-riscv.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index d6a3b6c..e121a59 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1144,6 +1144,8 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zvl256b", "zvl128b", check_implicit_always}, {"zvl128b", "zvl64b", check_implicit_always}, {"zvl64b", "zvl32b", check_implicit_always}, + {"zicntr", "zicsr", check_implicit_always}, + {"zihpm", "zicsr", check_implicit_always}, {"zcd", "d", check_implicit_always}, {"zcf", "f", check_implicit_always}, {"zfa", "f", check_implicit_always}, @@ -1263,12 +1265,14 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zicond", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zicntr", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 }, {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 }, {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, {"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, + {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, |